Merge tag 'drm-next-2019-07-16' of git://anongit.freedesktop.org/drm/drm (be8454af) · Commits · e / devices / android_kernel_fairphone_FP5

Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml

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			# SPDX-License-Identifier: GPL-2.0
			%YAML 1.2
			---
			$id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
			$schema: http://devicetree.org/meta-schemas/core.yaml#

			title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings

			maintainers:
			- Chen-Yu Tsai <wens@csie.org>
			- Maxime Ripard <maxime.ripard@bootlin.com>

			properties:
			"#address-cells": true
			"#size-cells": true

			compatible:
			const: allwinner,sun6i-a31-mipi-dsi

			reg:
			maxItems: 1

			interrupts:
			maxItems: 1

			clocks:
			items:
			- description: Bus Clock
			- description: Module Clock

			clock-names:
			items:
			- const: bus
			- const: mod

			resets:
			maxItems: 1

			phys:
			maxItems: 1

			phy-names:
			const: dphy

			port:
			type: object
			description:
			A port node with endpoint definitions as defined in
			Documentation/devicetree/bindings/media/video-interfaces.txt. That
			port should be the input endpoint, usually coming from the
			associated TCON.

			patternProperties:
			"^panel@[0-9]+$": true

			required:
			- "#address-cells"
			- "#size-cells"
			- compatible
			- reg
			- interrupts
			- clocks
			- clock-names
			- phys
			- phy-names
			- resets
			- port

			additionalProperties: false

			examples:
			- \|
			dsi0: dsi@1ca0000 {
			compatible = "allwinner,sun6i-a31-mipi-dsi";
			reg = <0x01ca0000 0x1000>;
			interrupts = <0 89 4>;
			clocks = <&ccu 23>, <&ccu 96>;
			clock-names = "bus", "mod";
			resets = <&ccu 4>;
			phys = <&dphy0>;
			phy-names = "dphy";
			#address-cells = <1>;
			#size-cells = <0>;

			panel@0 {
			compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
			reg = <0>;
			power-gpios = <&pio 1 7 0>; /* PB07 */
			reset-gpios = <&r_pio 0 5 1>; /* PL05 */
			backlight = <&pwm_bl>;
			};

			port {
			dsi0_in_tcon0: endpoint {
			remote-endpoint = <&tcon0_out_dsi0>;
			};
			};
			};

			...

Documentation/devicetree/bindings/display/arm,komeda.txt

+14 −9

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	@@ -7,10 +7,13 @@ Required properties:
	- clocks: A list of phandle + clock-specifier pairs, one for each entry		- clocks: A list of phandle + clock-specifier pairs, one for each entry
	in 'clock-names'		in 'clock-names'
	- clock-names: A list of clock names. It should contain:		- clock-names: A list of clock names. It should contain:
	- "mclk": for the main processor clock		- "aclk": for the main processor clock
	- "pclk": for the APB interface clock
	- #address-cells: Must be 1		- #address-cells: Must be 1
	- #size-cells: Must be 0		- #size-cells: Must be 0
			- iommus: configure the stream id to IOMMU, Must be configured if want to
			enable iommu in display. for how to configure this node please reference
			devicetree/bindings/iommu/arm,smmu-v3.txt,
			devicetree/bindings/iommu/iommu.txt

	Required properties for sub-node: pipeline@nq		Required properties for sub-node: pipeline@nq
	Each device contains one or two pipeline sub-nodes (at least one), each		Each device contains one or two pipeline sub-nodes (at least one), each
	@@ -20,7 +23,6 @@ pipeline node should provide properties:
	in 'clock-names'		in 'clock-names'
	- clock-names: should contain:		- clock-names: should contain:
	- "pxclk": pixel clock		- "pxclk": pixel clock
	- "aclk": AXI interface clock

	- port: each pipeline connect to an encoder input port. The connection is		- port: each pipeline connect to an encoder input port. The connection is
	modeled using the OF graph bindings specified in		modeled using the OF graph bindings specified in
	@@ -42,12 +44,15 @@ Example:
	compatible = "arm,mali-d71";		compatible = "arm,mali-d71";
	reg = <0xc00000 0x20000>;		reg = <0xc00000 0x20000>;
	interrupts = <0 168 4>;		interrupts = <0 168 4>;
	clocks = <&dpu_mclk>, <&dpu_aclk>;		clocks = <&dpu_aclk>;
	clock-names = "mclk", "pclk";		clock-names = "aclk";
			iommus = <&smmu 0>, <&smmu 1>, <&smmu 2>, <&smmu 3>,
			<&smmu 4>, <&smmu 5>, <&smmu 6>, <&smmu 7>,
			<&smmu 8>, <&smmu 9>;

	dp0_pipe0: pipeline@0 {		dp0_pipe0: pipeline@0 {
	clocks = <&fpgaosc2>, <&dpu_aclk>;		clocks = <&fpgaosc2>;
	clock-names = "pxclk", "aclk";		clock-names = "pxclk";
	reg = <0>;		reg = <0>;

	port {		port {
	@@ -58,8 +63,8 @@ Example:
	};		};

	dp0_pipe1: pipeline@1 {		dp0_pipe1: pipeline@1 {
	clocks = <&fpgaosc2>, <&dpu_aclk>;		clocks = <&fpgaosc2>;
	clock-names = "pxclk", "aclk";		clock-names = "pxclk";
	reg = <1>;		reg = <1>;

	port {		port {

Documentation/devicetree/bindings/display/bridge/renesas,lvds.txt

+15 −4

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	@@ -9,6 +9,7 @@ Required properties:
	- compatible : Shall contain one of		- compatible : Shall contain one of
	- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders		- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
	- "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders		- "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
			- "renesas,r8a774a1-lvds" for R8A774A1 (RZ/G2M) compatible LVDS encoders
	- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders		- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
	- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders		- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
	- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders		- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
	@@ -45,14 +46,24 @@ OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.

	Each port shall have a single endpoint.		Each port shall have a single endpoint.

			Optional properties:

			- renesas,companion : phandle to the companion LVDS encoder. This property is
			mandatory for the first LVDS encoder on D3 and E3 SoCs, and shall point to
			the second encoder to be used as a companion in dual-link mode. It shall not
			be set for any other LVDS encoder.


	Example:		Example:

	lvds0: lvds@feb90000 {		lvds0: lvds@feb90000 {
	compatible = "renesas,r8a7790-lvds";		compatible = "renesas,r8a77990-lvds";
	reg = <0 0xfeb90000 0 0x1c>;		reg = <0 0xfeb90000 0 0x20>;
	clocks = <&cpg CPG_MOD 726>;		clocks = <&cpg CPG_MOD 727>;
	resets = <&cpg 726>;		power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
			resets = <&cpg 727>;

			renesas,companion = <&lvds1>;

	ports {		ports {
	#address-cells = <1>;		#address-cells = <1>;

Documentation/devicetree/bindings/display/bridge/sii902x.txt

+41 −1

Original line number	Original line	Diff line number	Diff line
	@@ -9,6 +9,40 @@ Optional properties:
	about hotplug events.		about hotplug events.
	- reset-gpios: OF device-tree gpio specification for RST_N pin.		- reset-gpios: OF device-tree gpio specification for RST_N pin.

			HDMI audio properties:
			- #sound-dai-cells: <0> or <1>. <0> if only i2s or spdif pin
			is wired, <1> if the both are wired. HDMI audio is
			configured only if this property is found.
			- sil,i2s-data-lanes: Array of up to 4 integers with values of 0-3
			Each integer indicates which i2s pin is connected to which
			audio fifo. The first integer selects i2s audio pin for the
			first audio fifo#0 (HDMI channels 1&2), second for fifo#1
			(HDMI channels 3&4), and so on. There is 4 fifos and 4 i2s
			pins (SD0 - SD3). Any i2s pin can be connected to any fifo,
			but there can be no gaps. E.g. an i2s pin must be mapped to
			fifo#0 and fifo#1 before mapping a channel to fifo#2. Default
			value is <0>, describing SD0 pin beiging routed to hdmi audio
			fifo #0.
			- clocks: phandle and clock specifier for each clock listed in
			the clock-names property
			- clock-names: "mclk"
			Describes SII902x MCLK input. MCLK is used to produce
			HDMI audio CTS values. This property is required if
			"#sound-dai-cells"-property is present. This property follows
			Documentation/devicetree/bindings/clock/clock-bindings.txt
			consumer binding.

			If HDMI audio is configured the sii902x device becomes an I2S
			and/or spdif audio codec component (e.g a digital audio sink),
			that can be used in configuring a full audio devices with
			simple-card or audio-graph-card binding. See their binding
			documents on how to describe the way the sii902x device is
			connected to the rest of the audio system:
			Documentation/devicetree/bindings/sound/simple-card.txt
			Documentation/devicetree/bindings/sound/audio-graph-card.txt
			Note: In case of the audio-graph-card binding the used port
			index should be 3.

	Optional subnodes:		Optional subnodes:
	- video input: this subnode can contain a video input port node		- video input: this subnode can contain a video input port node
	to connect the bridge to a display controller output (See this		to connect the bridge to a display controller output (See this
	@@ -21,6 +55,12 @@ Example:
	compatible = "sil,sii9022";		compatible = "sil,sii9022";
	reg = <0x39>;		reg = <0x39>;
	reset-gpios = <&pioA 1 0>;		reset-gpios = <&pioA 1 0>;

			#sound-dai-cells = <0>;
			sil,i2s-data-lanes = < 0 1 2 >;
			clocks = <&mclk>;
			clock-names = "mclk";

	ports {		ports {
	#address-cells = <1>;		#address-cells = <1>;
	#size-cells = <0>;		#size-cells = <0>;

Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt

+6 −0

Original line number	Original line	Diff line number	Diff line
	@@ -28,6 +28,12 @@ Optional video port nodes:
	- port@1: Second LVDS input port		- port@1: Second LVDS input port
	- port@3: Second digital CMOS/TTL parallel output		- port@3: Second digital CMOS/TTL parallel output

			The device can operate in single-link mode or dual-link mode. In single-link
			mode, all pixels are received on port@0, and port@1 shall not contain any
			endpoint. In dual-link mode, even-numbered pixels are received on port@0 and
			odd-numbered pixels on port@1, and both port@0 and port@1 shall contain
			endpoints.

	Example:		Example:
	--------		--------