Merge "usb: dwc3: Disable USB2 internal retry for USB3.1 cores v1.70a and above"

		dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH_3(0),

			dwc->gen2_tx_de_emph3 & DWC31_TX_DEEMPH_MASK);

	/* set inter-packet gap 199.794ns to improve EL_23 margin */

	/*

	 * Set inter-packet gap 199.794ns to improve EL_23 margin.

	 *

	 * STAR 9001346572: Host: When a Single USB 2.0 Endpoint Receives NAKs Continuously, Host

	 * Stops Transfers to Other Endpoints. When an active endpoint that is not currently cached

	 * in the host controller is chosen to be cached to the same cache index as the endpoint

	 * that receives NAK, The endpoint that receives the NAK responses would be in continuous

	 * retry mode that would prevent it from getting evicted out of the host controller cache.

	 * This would prevent the new endpoint to get into the endpoint cache and therefore service

	 * to this endpoint is not done.

	 * The workaround is to disable lower layer LSP retrying the USB2.0 NAKed transfer. Forcing

	 * this to LSP upper layer allows next EP to evict the stuck EP from cache.

	 */

	if (dwc->revision >= DWC3_USB31_REVISION_170A) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);

		reg |= DWC3_GUCTL1_IP_GAP_ADD_ON(1);

		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);

		reg |= DWC3_GUCTL3_USB20_RETRY_DISABLE;

		dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);

	}

	return 0;

#define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)

/* Global User Control Register 3 */

#define DWC3_GUCTL3_USB20_RETRY_DISABLE		BIT(16)

#define DWC3_GUCTL3_SPLITDISABLE		BIT(14)

/* Device Configuration Register */