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Commit be5b2998 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Will Deacon
Browse files

arm64: capabilities: Add support for checks based on a list of MIDRs 



Add helpers for detecting an errata on list of midr ranges
of affected CPUs, with the same work around.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: default avatarDave Martin <dave.martin@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 1df31050

arch/arm64/include/asm/cpufeature.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -314,6 +314,7 @@ struct arm64_cpu_capabilities { 
			} * const fixed_revs;

			} * const fixed_revs;

		};

		};





		const struct midr_range *midr_range_list;

		struct {	/* Feature register checking */

		struct {	/* Feature register checking */

			u32 sys_reg;

			u32 sys_reg;

			u8 field_pos;

			u8 field_pos;

arch/arm64/include/asm/cputype.h

+9 −0
Original line number Original line Diff line number Diff line
@@ -147,6 +147,15 @@ static inline bool is_midr_in_range(u32 midr, struct midr_range const *range) 
				 range->rv_min, range->rv_max);

				 range->rv_min, range->rv_max);

}

}





static inline bool

is_midr_in_range_list(u32 midr, struct midr_range const *ranges)

{

	while (ranges->model)

		if (is_midr_in_range(midr, ranges++))

			return true;

	return false;

}



/*

/*

 * The CPU ID never changes at run time, so we might as well tell the

 * The CPU ID never changes at run time, so we might as well tell the

 * compiler that it's constant.  Use this function to read the CPU ID

 * compiler that it's constant.  Use this function to read the CPU ID

arch/arm64/kernel/cpu_errata.c

+44 −37
Original line number Original line Diff line number Diff line
@@ -40,6 +40,14 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) 
	return true;

	return true;

}

}





static bool __maybe_unused

is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,

			    int scope)

{

	WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());

	return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);

}



static bool __maybe_unused

static bool __maybe_unused

is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)

is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)

{

{
@@ -250,6 +258,10 @@ qcom_enable_link_stack_sanitization(const struct arm64_cpu_capabilities *entry) 
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,				\

	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,				\

	CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)

	CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)





#define CAP_MIDR_RANGE_LIST(list)				\

	.matches = is_affected_midr_range_list,			\

	.midr_range_list = list



/* Errata affecting a range of revisions of  given model variant */

/* Errata affecting a range of revisions of  given model variant */

#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)	 \

#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)	 \

	ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)

	ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
@@ -263,6 +275,35 @@ qcom_enable_link_stack_sanitization(const struct arm64_cpu_capabilities *entry) 
	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\

	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\

	CAP_MIDR_ALL_VERSIONS(model)

	CAP_MIDR_ALL_VERSIONS(model)





/* Errata affecting a list of midr ranges, with same work around */

#define ERRATA_MIDR_RANGE_LIST(midr_list)			\

	.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,			\

	CAP_MIDR_RANGE_LIST(midr_list)



#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR



/*

 * List of CPUs where we need to issue a psci call to

 * harden the branch predictor.

 */

static const struct midr_range arm64_bp_harden_smccc_cpus[] = {

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),

	MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),

	MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),

	{},

};



static const struct midr_range qcom_bp_harden_cpus[] = {

	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),

	MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),

	{},

};



#endif



const struct arm64_cpu_capabilities arm64_errata[] = {

const struct arm64_cpu_capabilities arm64_errata[] = {

#if	defined(CONFIG_ARM64_ERRATUM_826319) || \

#if	defined(CONFIG_ARM64_ERRATUM_826319) || \

	defined(CONFIG_ARM64_ERRATUM_827319) || \

	defined(CONFIG_ARM64_ERRATUM_827319) || \
@@ -406,51 +447,17 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

	{

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

		ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),

		.cpu_enable = enable_smccc_arch_workaround_1,

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

		.cpu_enable = enable_smccc_arch_workaround_1,

		.cpu_enable = enable_smccc_arch_workaround_1,

	},

	},

	{

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),

		ERRATA_MIDR_RANGE_LIST(qcom_bp_harden_cpus),

		.cpu_enable = enable_smccc_arch_workaround_1,

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),

		.cpu_enable = enable_smccc_arch_workaround_1,

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),

		.cpu_enable = qcom_enable_link_stack_sanitization,

		.cpu_enable = qcom_enable_link_stack_sanitization,

	},

	},

	{

	{

		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,

		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),

		ERRATA_MIDR_RANGE_LIST(qcom_bp_harden_cpus),

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),

		.cpu_enable = qcom_enable_link_stack_sanitization,

	},

	{

		.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),

		.cpu_enable = enable_smccc_arch_workaround_1,

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),

		.cpu_enable = enable_smccc_arch_workaround_1,

	},

	},

#endif

#endif

	{

	{

arch/arm64/kernel/cpufeature.c

+6 −4
Original line number Original line Diff line number Diff line
@@ -882,6 +882,11 @@ static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 
static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,

static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,

				int scope)

				int scope)

{

{

	/* List of CPUs that are not vulnerable and don't need KPTI */

	static const struct midr_range kpti_safe_list[] = {

		MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),

		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),

	};

	char const *str = "command line option";

	char const *str = "command line option";





	/*

	/*
@@ -906,11 +911,8 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 
		return true;

		return true;





	/* Don't force KPTI for CPUs that are not vulnerable */

	/* Don't force KPTI for CPUs that are not vulnerable */

	switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {

	if (is_midr_in_range_list(read_cpuid_id(), kpti_safe_list))

	case MIDR_CAVIUM_THUNDERX2:

	case MIDR_BRCM_VULCAN:

		return false;

		return false;

	}





	/* Defer to CPU feature registers */

	/* Defer to CPU feature registers */

	return !has_cpuid_feature(entry, scope);

	return !has_cpuid_feature(entry, scope);