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Commit be3989d9 authored by Peter Seiderer's avatar Peter Seiderer Committed by Greg Kroah-Hartman
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wifi: ath9k: fix AR9003 mac hardware hang check register offset calculation 



[ Upstream commit 3e56c80931c7615250fe4bf83f93b57881969266 ]

Fix ath9k_hw_verify_hang()/ar9003_hw_detect_mac_hang() register offset
calculation (do not overflow the shift for the second register/queues
above five, use the register layout described in the comments above
ath9k_hw_verify_hang() instead).

Fixes: 222e0483 ("ath9k: Fix MAC HW hang check for AR9003")

Reported-by: default avatarGregg Wonderly <greggwonderly@seqtechllc.com>
Link: https://lore.kernel.org/linux-wireless/E3A9C354-0CB7-420C-ADEF-F0177FB722F4@seqtechllc.com/


Signed-off-by: default avatarPeter Seiderer <ps.report@gmx.net>
Acked-by: default avatarToke Høiland-Jørgensen <toke@toke.dk>
Reviewed-by: default avatarSimon Horman <simon.horman@corigine.com>
Signed-off-by: default avatarKalle Valo <quic_kvalo@quicinc.com>
Link: https://lore.kernel.org/r/20230422212423.26065-1-ps.report@gmx.net


Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 717e4277

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+18 −9
Original line number Diff line number Diff line
@@ -1099,17 +1099,22 @@ static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue) 
{

	u32 dma_dbg_chain, dma_dbg_complete;

	u8 dcu_chain_state, dcu_complete_state;

	unsigned int dbg_reg, reg_offset;

	int i;



	for (i = 0; i < NUM_STATUS_READS; i++) {

		if (queue < 6)

			dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);

		else

			dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);

	if (queue < 6) {

		dbg_reg = AR_DMADBG_4;

		reg_offset = queue * 5;

	} else {

		dbg_reg = AR_DMADBG_5;

		reg_offset = (queue - 6) * 5;

	}



	for (i = 0; i < NUM_STATUS_READS; i++) {

		dma_dbg_chain = REG_READ(ah, dbg_reg);

		dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);



		dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;

		dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f;

		dcu_complete_state = dma_dbg_complete & 0x3;



		if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
@@ -1128,6 +1133,7 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah) 
	u8 dcu_chain_state, dcu_complete_state;

	bool dcu_wait_frdone = false;

	unsigned long chk_dcu = 0;

	unsigned int reg_offset;

	unsigned int i = 0;



	dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
@@ -1139,12 +1145,15 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah) 
		goto exit;



	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {

		if (i < 6)

		if (i < 6) {

			chk_dbg = dma_dbg_4;

		else

			reg_offset = i * 5;

		} else {

			chk_dbg = dma_dbg_5;

			reg_offset = (i - 6) * 5;

		}



		dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;

		dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f;

		if (dcu_chain_state == 0x6) {

			dcu_wait_frdone = true;

			chk_dcu |= BIT(i);