Merge "msm: ipa3: get ipa clk for issuing uc cmds" (be1ce744) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/platform/msm/ipa/ipa_v3/ipa_uc.c

+8 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1216,6 +1216,8 @@ int ipa3_uc_setup_event_ring(void)
	(u32) ((ring->phys_base & 0xFFFFFFFF00000000) >> 32);		(u32) ((ring->phys_base & 0xFFFFFFFF00000000) >> 32);
	ring_info->event.ring_size = IPA_UC_EVENT_RING_SIZE;		ring_info->event.ring_size = IPA_UC_EVENT_RING_SIZE;

			IPA_ACTIVE_CLIENTS_INC_SIMPLE();

	res = ipa3_uc_send_cmd((u32)(cmd.phys_base),		res = ipa3_uc_send_cmd((u32)(cmd.phys_base),
	IPA_CPU_2_HW_CMD_SETUP_EVENT_RING, 0,		IPA_CPU_2_HW_CMD_SETUP_EVENT_RING, 0,
	false, 10 * HZ);		false, 10 * HZ);
	@@ -1245,6 +1247,7 @@ int ipa3_uc_setup_event_ring(void)
	free_cmd:		free_cmd:
	dma_free_coherent(ipa3_ctx->uc_pdev,		dma_free_coherent(ipa3_ctx->uc_pdev,
	cmd.size, cmd.base, cmd.phys_base);		cmd.size, cmd.base, cmd.phys_base);
			IPA_ACTIVE_CLIENTS_DEC_SIMPLE();
	return res;		return res;
	}		}

	@@ -1287,6 +1290,7 @@ int ipa3_uc_quota_monitor(uint64_t quota)
	quota_info->params.WdiQM.info.Interval =		quota_info->params.WdiQM.info.Interval =
	IPA_UC_MON_INTERVAL;		IPA_UC_MON_INTERVAL;

			IPA_ACTIVE_CLIENTS_INC_SIMPLE();
	res = ipa3_uc_send_cmd((u32)(cmd.phys_base),		res = ipa3_uc_send_cmd((u32)(cmd.phys_base),
	IPA_CPU_2_HW_CMD_QUOTA_MONITORING,		IPA_CPU_2_HW_CMD_QUOTA_MONITORING,
	IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,		IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
	@@ -1307,6 +1311,7 @@ int ipa3_uc_quota_monitor(uint64_t quota)

	free_cmd:		free_cmd:
	dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);		dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
			IPA_ACTIVE_CLIENTS_DEC_SIMPLE();

	return res;		return res;
	}		}
	@@ -1388,6 +1393,8 @@ int ipa3_uc_bw_monitor(struct ipa_wdi_bw_info *info)
	bw_info->params.WdiBw.info.Interval =		bw_info->params.WdiBw.info.Interval =
	IPA_UC_MON_INTERVAL;		IPA_UC_MON_INTERVAL;

			IPA_ACTIVE_CLIENTS_INC_SIMPLE();

	res = ipa3_uc_send_cmd((u32)(cmd.phys_base),		res = ipa3_uc_send_cmd((u32)(cmd.phys_base),
	IPA_CPU_2_HW_CMD_BW_MONITORING,		IPA_CPU_2_HW_CMD_BW_MONITORING,
	IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,		IPA_HW_2_CPU_OFFLOAD_CMD_STATUS_SUCCESS,
	@@ -1402,6 +1409,7 @@ int ipa3_uc_bw_monitor(struct ipa_wdi_bw_info *info)

	free_cmd:		free_cmd:
	dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);		dma_free_coherent(ipa3_ctx->uc_pdev, cmd.size, cmd.base, cmd.phys_base);
			IPA_ACTIVE_CLIENTS_DEC_SIMPLE();

	return res;		return res;
	}		}