clk: qcom: clk-alpha-pll: add support to reconfigure PLLs during prepare (bd0b7595) · Commits · e / devices / android_kernel_fairphone_FP5

Under some circumstances, such as during subsystem restart, the registers for a clock controller may be reset to hardware default values. Add support to reconfigure a Lucid PLL during clk_prepare in the case that the CAL_L_VAL is found to be 0 before performing calibration. Change-Id: Idef3c42dfb32748ec40f89a9dab9f6ab86e293f6 Signed-off-by:

David Collins <collinsd@codeaurora.org>

drivers/clk/qcom/clk-alpha-pll.c

+14 −0

Original line number	Diff line number	Diff line
		@@ -1593,6 +1593,20 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw)
		if (regval & LUCID_PCAL_DONE)
		return 0;

		if (pll->config) {
		/*
		* Reconfigure the PLL if CAL_L_VAL is 0 (which implies that all
		* clock controller registers have been reset).
		*/
		regmap_read(pll->clkr.regmap, PLL_CAL_L_VAL(pll), &regval);
		if (!regval) {
		pr_debug("reconfiguring %s after it was reset\n",
		clk_hw_get_name(hw));
		clk_lucid_pll_configure(pll, pll->clkr.regmap,
		pll->config);
		}
		}

		p = clk_hw_get_parent(hw);
		if (!p)
		return -EINVAL;