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Commit bcf6f1e9 authored by Christian König's avatar Christian König Committed by Alex Deucher
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drm/radeon/uvd: revert lower msg&fb buffer requirements on UVD3



This only seem to work for H.264 but not for VC-1 streams.

Need to investigate further why exactly.

This reverts commit 4b40e592.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5510f124
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+1 −2
Original line number Diff line number Diff line
@@ -85,9 +85,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
		   VRAM, also but everything into VRAM on AGP cards to avoid
		   image corruptions */
		if (p->ring == R600_RING_TYPE_UVD_INDEX &&
		    p->rdev->family < CHIP_PALM &&
		    (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {

			/* TODO: is this still needed for NI+ ? */
			p->relocs[i].lobj.domain =
				RADEON_GEM_DOMAIN_VRAM;

+2 −1
Original line number Diff line number Diff line
@@ -476,7 +476,8 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
		return -EINVAL;
	}

	if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) &&
	/* TODO: is this still necessary on NI+ ? */
	if ((cmd == 0 || cmd == 0x3) &&
	    (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
		DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
			  start, end);
+2 −2
Original line number Diff line number Diff line
@@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev)
	/* enable VCPU clock */
	WREG32(UVD_VCPU_CNTL,  1 << 9);

	/* enable UMC and NC0 */
	WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) | (1 << 13)));
	/* enable UMC */
	WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));

	/* boot up the VCPU */
	WREG32(UVD_SOFT_RESET, 0);