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Commit bcaad532 authored by Manasi Navare's avatar Manasi Navare Committed by Paulo Zanoni
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drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as... 


drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines

The register value of Divider Ratio for high speed divider
(hsdiv_ratio) in MG_CLKTOP2_HSCLKCTL_PORT register is not same as the
actual numerical value of the divider. So this patch implements
separate divider value defines for that field.
icl_mg_pll_find_divisors() can use these defines instead of magic
register values.

The new defines are going to be used in the next patch.

v2 (from Paulo):
 * Rebase.
 * Make it look a little more like the rest of our code.
v3 (from Paulo):
 * Make hsdiv u32 now that it's a bit field (José).

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Suggested-by: default avatarJames Ausmus <james.ausmus@intel.com>
Signed-off-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180817215209.29133-1-paulo.r.zanoni@intel.com
parent 35a5fd9e

drivers/gpu/drm/i915/i915_reg.h

+4 −1
Original line number Diff line number Diff line
@@ -9391,8 +9391,11 @@ enum skl_power_gate { 
#define   MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK	(0x1 << 16)

#define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x)	((x) << 14)

#define   MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK	(0x3 << 14)

#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x)		((x) << 12)

#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK		(0x3 << 12)

#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2		(0 << 12)

#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3		(1 << 12)

#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5		(2 << 12)

#define   MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7		(3 << 12)

#define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x)		((x) << 8)

#define   MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK		(0xf << 8)

#define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \

drivers/gpu/drm/i915/intel_dpll_mgr.c

+7 −6
Original line number Diff line number Diff line
@@ -2643,7 +2643,8 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, 


		for (div2 = 10; div2 > 0; div2--) {

			int dco = div1 * div2 * clock_khz * 5;

			int a_divratio, tlinedrv, inputsel, hsdiv;

			int a_divratio, tlinedrv, inputsel;

			u32 hsdiv;



			if (dco < dco_min_freq || dco > dco_max_freq)

				continue;
@@ -2662,16 +2663,16 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, 
				MISSING_CASE(div1);

				/* fall through */

			case 2:

				hsdiv = 0;

				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;

				break;

			case 3:

				hsdiv = 1;

				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;

				break;

			case 5:

				hsdiv = 2;

				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;

				break;

			case 7:

				hsdiv = 3;

				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;

				break;

			}
@@ -2685,7 +2686,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, 
			state->mg_clktop2_hsclkctl =

				MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |

				MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |

				MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) |

				hsdiv |

				MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);



			return true;