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Commit bc3c03cc authored by Julien Thierry's avatar Julien Thierry Committed by Catalin Marinas
Browse files

arm64: Enable the support of pseudo-NMIs 



Add a build option and a command line parameter to build and enable the
support of pseudo-NMIs.

Signed-off-by: default avatarJulien Thierry <julien.thierry@arm.com>
Suggested-by: default avatarDaniel Thompson <daniel.thompson@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent c25349fd

Documentation/admin-guide/kernel-parameters.txt

+5 −0
Original line number Diff line number Diff line
@@ -1831,6 +1831,11 @@ 
			to let secondary kernels in charge of setting up

			LPIs.



	irqchip.gicv3_pseudo_nmi= [ARM64]

			Enables support for pseudo-NMIs in the kernel. This

			requires the kernel to be built with

			CONFIG_ARM64_PSEUDO_NMI.



	irqfixup	[HW]

			When an interrupt is not handled search all handlers

			for it. Intended to get systems with badly broken

arch/arm64/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -1327,6 +1327,20 @@ config ARM64_MODULE_PLTS 
	bool

	select HAVE_MOD_ARCH_SPECIFIC



config ARM64_PSEUDO_NMI

	bool "Support for NMI-like interrupts"

	select CONFIG_ARM_GIC_V3

	help

	  Adds support for mimicking Non-Maskable Interrupts through the use of

	  GIC interrupt priority. This support requires version 3 or later of

	  Arm GIC.



	  This high priority configuration for interrupts needs to be

	  explicitly enabled by setting the kernel parameter

	  "irqchip.gicv3_pseudo_nmi" to 1.



	  If unsure, say N



config RELOCATABLE

	bool

	help

arch/arm64/kernel/cpufeature.c

+9 −1
Original line number Diff line number Diff line
@@ -1207,10 +1207,18 @@ static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap) 
#endif /* CONFIG_ARM64_PTR_AUTH */



#ifdef CONFIG_ARM64_PSEUDO_NMI

static bool enable_pseudo_nmi;



static int __init early_enable_pseudo_nmi(char *p)

{

	return strtobool(p, &enable_pseudo_nmi);

}

early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);



static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,

				   int scope)

{

	return false;

	return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);

}

#endif