Merge 5.3 into android-mainline (bc378eba) · Commits · e / devices / android_kernel_fairphone_FP5

Documentation/riscv/boot-image-header.txt

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Original line number	Diff line number	Diff line
		@@ -18,7 +18,7 @@ The following 64-byte header is present in decompressed Linux kernel image.
		u32 res1 = 0; /* Reserved */
		u64 res2 = 0; /* Reserved */
		u64 magic = 0x5643534952; /* Magic number, little endian, "RISCV" */
		u32 res3; /* Reserved for additional RISC-V specific header */
		u32 magic2 = 0x56534905; /* Magic number 2, little endian, "RSC\x05" */
		u32 res4; /* Reserved for PE COFF offset */

		This header format is compliant with PE/COFF header and largely inspired from
		@@ -37,13 +37,14 @@ Notes:
		Bits 16:31 - Major version

		This preserves compatibility across newer and older version of the header.
		The current version is defined as 0.1.
		The current version is defined as 0.2.

		- res3 is reserved for offset to any other additional fields. This makes the
		header extendible in future. One example would be to accommodate ISA
		extension for RISC-V in future. For current version, it is set to be zero.
		- The "magic" field is deprecated as of version 0.2. In a future
		release, it may be removed. This originally should have matched up
		with the ARM64 header "magic" field, but unfortunately does not.
		The "magic2" field replaces it, matching up with the ARM64 header.

		- In current header, the flag field has only one field.
		- In current header, the flags field has only one field.
		Bit 0: Kernel endianness. 1 if BE, 0 if LE.

		- Image size is mandatory for boot loader to load kernel image. Booting will

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Original line number	Diff line number	Diff line
		@@ -17699,8 +17699,7 @@ F: include/uapi/linux/dqblk_xfs.h
		F: include/uapi/linux/fsmap.h

		XILINX AXI ETHERNET DRIVER
		M: Anirudha Sarangi <anirudh@xilinx.com>
		M: John Linn <John.Linn@xilinx.com>
		M: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
		S: Maintained
		F: drivers/net/ethernet/xilinx/xilinx_axienet*

+1 −1

+6 −6

Original line number	Diff line number	Diff line
		@@ -3,7 +3,8 @@
		#ifndef __ASM_IMAGE_H
		#define __ASM_IMAGE_H

		#define RISCV_IMAGE_MAGIC "RISCV"
		#define RISCV_IMAGE_MAGIC "RISCV\0\0\0"
		#define RISCV_IMAGE_MAGIC2 "RSC\x05"

		#define RISCV_IMAGE_FLAG_BE_SHIFT 0
		#define RISCV_IMAGE_FLAG_BE_MASK 0x1
		@@ -23,7 +24,7 @@
		#define __HEAD_FLAGS (__HEAD_FLAG(BE))

		#define RISCV_HEADER_VERSION_MAJOR 0
		#define RISCV_HEADER_VERSION_MINOR 1
		#define RISCV_HEADER_VERSION_MINOR 2

		#define RISCV_HEADER_VERSION (RISCV_HEADER_VERSION_MAJOR << 16 \| \
		RISCV_HEADER_VERSION_MINOR)
		@@ -39,9 +40,8 @@
		* @version: version
		* @res1: reserved
		* @res2: reserved
		* @magic: Magic number
		* @res3: reserved (will be used for additional RISC-V specific
		* header)
		* @magic: Magic number (RISC-V specific; deprecated)
		* @magic2: Magic number 2 (to match the ARM64 'magic' field pos)
		* @res4: reserved (will be used for PE COFF offset)
		*
		* The intention is for this header format to be shared between multiple
		@@ -58,7 +58,7 @@ struct riscv_image_header {
		u32 res1;
		u64 res2;
		u64 magic;
		u32 res3;
		u32 magic2;
		u32 res4;
		};
		#endif /* __ASSEMBLY__ */

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