Loading drivers/clk/qcom/gcc-blair.c +2 −0 Original line number Diff line number Diff line Loading @@ -4281,6 +4281,8 @@ static const struct qcom_reset_map gcc_blair_resets[] = { [GCC_SDCC2_BCR] = { 0x1e000 }, [GCC_UFS_PHY_BCR] = { 0x45000 }, [GCC_USB30_PRIM_BCR] = { 0x1a000 }, [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 }, [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, [GCC_VCODEC0_BCR] = { 0x58094 }, [GCC_VENUS_BCR] = { 0x58078 }, Loading include/dt-bindings/clock/qcom,gcc-blair.h +2 −0 Original line number Diff line number Diff line Loading @@ -216,5 +216,7 @@ #define GCC_VCODEC0_BCR 16 #define GCC_VENUS_BCR 17 #define GCC_VIDEO_INTERFACE_BCR 18 #define GCC_USB3_DP_PHY_PRIM_BCR 19 #define GCC_USB3_PHY_PRIM_SP0_BCR 20 #endif Loading
drivers/clk/qcom/gcc-blair.c +2 −0 Original line number Diff line number Diff line Loading @@ -4281,6 +4281,8 @@ static const struct qcom_reset_map gcc_blair_resets[] = { [GCC_SDCC2_BCR] = { 0x1e000 }, [GCC_UFS_PHY_BCR] = { 0x45000 }, [GCC_USB30_PRIM_BCR] = { 0x1a000 }, [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 }, [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, [GCC_VCODEC0_BCR] = { 0x58094 }, [GCC_VENUS_BCR] = { 0x58078 }, Loading
include/dt-bindings/clock/qcom,gcc-blair.h +2 −0 Original line number Diff line number Diff line Loading @@ -216,5 +216,7 @@ #define GCC_VCODEC0_BCR 16 #define GCC_VENUS_BCR 17 #define GCC_VIDEO_INTERFACE_BCR 18 #define GCC_USB3_DP_PHY_PRIM_BCR 19 #define GCC_USB3_PHY_PRIM_SP0_BCR 20 #endif