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Commit bbe33b72 authored by Treehugger Robot's avatar Treehugger Robot
Browse files

Merge changes I407c2796,If3f36646,Ia03ea493,I5f0e742b,Ibe09c3b1, ... into android11-5.4-lts 

* changes:
  Revert "netfilter: conntrack: allow sctp hearbeat after connection re-use"
  Revert "netfilter: conntrack: don't refresh sctp entries in closed state"
  Revert "netfilter: handle the connecting collision properly in nf_conntrack_proto_sctp"
  Merge 5.4.258 into android11-5.4-lts
  Reapply "netfilter: conntrack: don't refresh sctp entries in closed state"
  Reapply "netfilter: conntrack: allow sctp hearbeat after connection re-use"
parents 18911434 6eb76db1

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 5

PATCHLEVEL = 4

SUBLEVEL = 257

SUBLEVEL = 258

EXTRAVERSION =

NAME = Kleptomaniac Octopus

arch/parisc/include/asm/ldcw.h

+20 −16
Original line number Diff line number Diff line
@@ -2,7 +2,6 @@ 
#ifndef __PARISC_LDCW_H

#define __PARISC_LDCW_H



#ifndef CONFIG_PA20

/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,

   and GCC only guarantees 8-byte alignment for stack locals, we can't

   be assured of 16-byte alignment for atomic lock data even if we
@@ -11,6 +10,21 @@ 
   type and dynamically select the 16-byte aligned int from the array

   for the semaphore. */



/* From: "Jim Hull" <jim.hull of hp.com>

   I've attached a summary of the change, but basically, for PA 2.0, as

   long as the ",CO" (coherent operation) completer is implemented, then the

   16-byte alignment requirement for ldcw and ldcd is relaxed, and instead

   they only require "natural" alignment (4-byte for ldcw, 8-byte for

   ldcd).



   Although the cache control hint is accepted by all PA 2.0 processors,

   it is only implemented on PA8800/PA8900 CPUs. Prior PA8X00 CPUs still

   require 16-byte alignment. If the address is unaligned, the operation

   of the instruction is undefined. The ldcw instruction does not generate

   unaligned data reference traps so misaligned accesses are not detected.

   This hid the problem for years. So, restore the 16-byte alignment dropped

   by Kyle McMartin in "Remove __ldcw_align for PA-RISC 2.0 processors". */



#define __PA_LDCW_ALIGNMENT	16

#define __PA_LDCW_ALIGN_ORDER	4

#define __ldcw_align(a) ({					\
@@ -19,22 +33,12 @@ 
		& ~(__PA_LDCW_ALIGNMENT - 1);			\

	(volatile unsigned int *) __ret;			\

})

#define __LDCW	"ldcw"



#else /*CONFIG_PA20*/

/* From: "Jim Hull" <jim.hull of hp.com>

   I've attached a summary of the change, but basically, for PA 2.0, as

   long as the ",CO" (coherent operation) completer is specified, then the

   16-byte alignment requirement for ldcw and ldcd is relaxed, and instead

   they only require "natural" alignment (4-byte for ldcw, 8-byte for

   ldcd). */



#define __PA_LDCW_ALIGNMENT	4

#define __PA_LDCW_ALIGN_ORDER	2

#define __ldcw_align(a) (&(a)->slock)

#ifdef CONFIG_PA20

#define __LDCW	"ldcw,co"



#endif /*!CONFIG_PA20*/

#else

#define __LDCW	"ldcw"

#endif



/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.

   We don't explicitly expose that "*a" may be written as reload

arch/parisc/include/asm/spinlock_types.h

+0 −5
Original line number Diff line number Diff line
@@ -3,13 +3,8 @@ 
#define __ASM_SPINLOCK_TYPES_H



typedef struct {

#ifdef CONFIG_PA20

	volatile unsigned int slock;

# define __ARCH_SPIN_LOCK_UNLOCKED { 1 }

#else

	volatile unsigned int lock[4];

# define __ARCH_SPIN_LOCK_UNLOCKED	{ { 1, 1, 1, 1 } }

#endif

} arch_spinlock_t;



typedef struct {

drivers/base/regmap/regcache-rbtree.c

+2 −1
Original line number Diff line number Diff line
@@ -453,7 +453,8 @@ static int regcache_rbtree_write(struct regmap *map, unsigned int reg, 
		if (!rbnode)

			return -ENOMEM;

		regcache_rbtree_set_register(map, rbnode,

					     reg - rbnode->base_reg, value);

					     (reg - rbnode->base_reg) / map->reg_stride,

					     value);

		regcache_rbtree_insert(map, &rbtree_ctx->root, rbnode);

		rbtree_ctx->cached_rbnode = rbnode;

	}

drivers/gpio/gpio-aspeed.c

+1 −1
Original line number Diff line number Diff line
@@ -967,7 +967,7 @@ static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 
	else if (param == PIN_CONFIG_BIAS_DISABLE ||

			param == PIN_CONFIG_BIAS_PULL_DOWN ||

			param == PIN_CONFIG_DRIVE_STRENGTH)

		return pinctrl_gpio_set_config(offset, config);

		return pinctrl_gpio_set_config(chip->base + offset, config);

	else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||

			param == PIN_CONFIG_DRIVE_OPEN_SOURCE)

		/* Return -ENOTSUPP to trigger emulation, as per datasheet */