Merge "ARM: dts: msm: Add the APPS SMMU device for direwolf"

#include "direwolf-pm.dtsi"

#include "direwolf-gdsc.dtsi"

#include "direwolf-ion.dtsi"

#include "msm-arm-smmu-direwolf.dtsi"

&gcc_emac0_gdsc {

	status = "ok";

#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {

	apps_smmu: apps-smmu@15000000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x15000000 0x100000>,

			<0x15182000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,use-3-lvl-tables;

		#global-interrupts = <2>;

		#size-cells = <1>;

		#address-cells = <1>;

		ranges;

		interrupts =	<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;

		interconnects = <&gem_noc MASTER_APPSS_PROC

				&config_noc SLAVE_IMEM_CFG>;

	};

	apps_iommu_test_device {

		compatible = "iommu-debug-test";

		iommus = <&apps_smmu 0x0 0>;

		qcom,iommu-dma = "disabled";

		status = "disabled";

	};

	apps_iommu_coherent_test_device {

		compatible = "iommu-debug-test";

		iommus = <&apps_smmu 0x1 0>;

		qcom,iommu-dma = "disabled";

		dma-coherent;

		status = "disabled";

	};

};