+4
−3
Loading
Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more
A frame trigger with posted start may have two frames
in wait state due to irq disable on that CPU. In such
case, frame_done count can reach till 2. Allowing count
only till 1, can cause the release_fence trigger miss
and a buffer is held by DPU driver.
Change-Id: I42c10b064ebcaff136591975f3010c11f99a0731
Signed-off-by:
Dhaval Patel <pdhaval@codeaurora.org>