Merge "Add support for EMMC storage type" (bba465d5) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/mmc/host/Kconfig

+2 −2

Original line number	Diff line number	Diff line
		@@ -1043,7 +1043,7 @@ config SDC_QTI
		MMC upstream driver.

		config MMC_CQHCI_CRYPTO
		bool "CQHCI Crypto Engine Support"
		tristate "CQHCI Crypto Engine Support"
		depends on MMC_CQHCI && BLK_INLINE_ENCRYPTION
		help
		Enable Crypto Engine Support in CQHCI.
		@@ -1052,7 +1052,7 @@ config MMC_CQHCI_CRYPTO
		operations on data being transferred to/from the device.

		config MMC_CQHCI_CRYPTO_QTI
		bool "Vendor specific CQHCI Crypto Engine Support"
		tristate "Vendor specific CQHCI Crypto Engine Support"
		depends on MMC_CQHCI_CRYPTO
		help
		Enable Vendor Crypto Engine Support in CQHCI

+23 −2

Original line number	Diff line number	Diff line
		@@ -243,6 +243,8 @@ int cqhci_crypto_qti_init_crypto(struct cqhci_host *host,
		{
		int err = 0;
		struct resource *cqhci_ice_memres = NULL;
		struct resource *hwkm_ice_memres = NULL;
		void __iomem *hwkm_ice_mmio = NULL;

		cqhci_ice_memres = platform_get_resource_byname(host->pdev,
		IORESOURCE_MEM,
		@@ -261,6 +263,24 @@ int cqhci_crypto_qti_init_crypto(struct cqhci_host *host,
		return PTR_ERR(host->icemmio);
		}

		hwkm_ice_memres = platform_get_resource_byname(host->pdev,
		IORESOURCE_MEM,
		"cqhci_ice_hwkm");

		if (!hwkm_ice_memres) {
		pr_err("%s: Either no entry in dtsi or no memory available for IORESOURCE\n",
		__func__);
		} else {
		hwkm_ice_mmio = devm_ioremap_resource(&host->pdev->dev,
		hwkm_ice_memres);
		if (IS_ERR(hwkm_ice_mmio)) {
		err = PTR_ERR(hwkm_ice_mmio);
		pr_err("%s: Error = %d mapping HWKM memory\n",
		__func__, err);
		return err;
		}
		}

		err = cqhci_host_init_crypto_qti_spec(host, &cqhci_crypto_qti_ksm_ops);
		if (err) {
		pr_err("%s: Error initiating crypto capabilities, err %d\n",
		@@ -268,8 +288,9 @@ int cqhci_crypto_qti_init_crypto(struct cqhci_host *host,
		return err;
		}

		err = crypto_qti_init_crypto(&host->pdev->dev,
		host->icemmio, (void **)&host->crypto_vops->priv);
		err = crypto_qti_init_crypto(&host->pdev->dev, host->icemmio,
		hwkm_ice_mmio,
		(void **)&host->crypto_vops->priv);
		if (err) {
		pr_err("%s: Error initiating crypto, err %d\n",
		__func__, err);

+2 −1

Original line number	Diff line number	Diff line
		@@ -9,10 +9,11 @@
		#ifndef _CQHCI_CRYPTO_H
		#define _CQHCI_CRYPTO_H

		#ifdef CONFIG_MMC_CQHCI_CRYPTO
		#include <linux/mmc/host.h>
		#include "cqhci.h"

		#ifdef CONFIG_MMC_CQHCI_CRYPTO

		static inline int cqhci_num_keyslots(struct cqhci_host *host)
		{
		return host->crypto_capabilities.config_count + 1;

+7 −6

Original line number	Diff line number	Diff line
		@@ -276,10 +276,8 @@ static void __cqhci_enable(struct cqhci_host *cq_host)
		if (cq_host->caps & CQHCI_TASK_DESC_SZ_128)
		cqcfg \|= CQHCI_TASK_DESC_SZ;

		if (cqhci_host_is_crypto_supported(cq_host)) {
		cqhci_crypto_enable(cq_host);
		if (cqhci_host_is_crypto_supported(cq_host))
		cqcfg \|= CQHCI_ICE_ENABLE;
		}

		cqhci_writel(cq_host, cqcfg, CQHCI_CFG);

		@@ -314,9 +312,6 @@ static void __cqhci_disable(struct cqhci_host *cq_host)
		{
		u32 cqcfg;

		if (cqhci_host_is_crypto_supported(cq_host))
		cqhci_crypto_disable(cq_host);

		cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
		cqcfg &= ~CQHCI_ENABLE;
		cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
		@@ -367,6 +362,9 @@ static int cqhci_enable(struct mmc_host mmc, struct mmc_card card)
		return err;
		}

		if (cqhci_host_is_crypto_supported(cq_host))
		cqhci_crypto_enable(cq_host);

		__cqhci_enable(cq_host);

		cq_host->enabled = true;
		@@ -418,6 +416,9 @@ static void cqhci_disable(struct mmc_host *mmc)

		cqhci_off(mmc);

		if (cqhci_host_is_crypto_supported(cq_host))
		cqhci_crypto_disable(cq_host);

		__cqhci_disable(cq_host);

		dmam_free_coherent(mmc_dev(mmc), cq_host->data_size,

+22 −2

Original line number	Diff line number	Diff line
		@@ -267,6 +267,8 @@ int ufshcd_crypto_qti_init_crypto(struct ufs_hba *hba,
		struct platform_device *pdev = to_platform_device(hba->dev);
		void __iomem *mmio_base;
		struct resource *mem_res;
		void __iomem *hwkm_ice_mmio = NULL;
		struct resource *hwkm_ice_memres = NULL;

		mem_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
		"ufs_ice");
		@@ -276,6 +278,24 @@ int ufshcd_crypto_qti_init_crypto(struct ufs_hba *hba,
		return PTR_ERR(mmio_base);
		}

		hwkm_ice_memres = platform_get_resource_byname(pdev, IORESOURCE_MEM,
		"ufs_ice_hwkm");

		if (!hwkm_ice_memres) {
		pr_err("%s: Either no entry in dtsi or no memory available for IORESOURCE\n",
		__func__);
		} else {
		hwkm_ice_mmio = devm_ioremap_resource(hba->dev,
		hwkm_ice_memres);

		if (IS_ERR(hwkm_ice_mmio)) {
		err = PTR_ERR(hwkm_ice_mmio);
		pr_err("%s: Error = %d mapping HWKM memory\n",
		__func__, err);
		return err;
		}
		}

		err = ufshcd_hba_init_crypto_qti_spec(hba, &ufshcd_crypto_qti_ksm_ops);
		if (err) {
		pr_err("%s: Error initiating crypto capabilities, err %d\n",
		@@ -283,8 +303,8 @@ int ufshcd_crypto_qti_init_crypto(struct ufs_hba *hba,
		return err;
		}

		err = crypto_qti_init_crypto(hba->dev,
		mmio_base, (void **)&hba->crypto_vops->priv);
		err = crypto_qti_init_crypto(hba->dev, mmio_base, hwkm_ice_mmio,
		(void **)&hba->crypto_vops->priv);
		if (err) {
		pr_err("%s: Error initiating crypto, err %d\n",
		__func__, err);