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Commit bb97be23 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'iommu-updates-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull IOMMU updates from Joerg Roedel:

 - A big cleanup and optimization patch-set for the Tegra GART driver

 - Documentation updates and fixes for the IOMMU-API

 - Support for page request in Intel VT-d scalable mode

 - Intel VT-d dma_[un]map_resource() support

 - Updates to the ATS enabling code for PCI (acked by Bjorn) and Intel
   VT-d to align with the latest version of the ATS spec

 - Relaxed IRQ source checking in the Intel VT-d driver for some aliased
   devices, needed for future devices which send IRQ messages from more
   than on request-ID

 - IRQ remapping driver for Hyper-V

 - Patches to make generic IOVA and IO-Page-Table code usable outside of
   the IOMMU code

 - Various other small fixes and cleanups

* tag 'iommu-updates-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (60 commits)
  iommu/vt-d: Get domain ID before clear pasid entry
  iommu/vt-d: Fix NULL pointer reference in intel_svm_bind_mm()
  iommu/vt-d: Set context field after value initialized
  iommu/vt-d: Disable ATS support on untrusted devices
  iommu/mediatek: Fix semicolon code style issue
  MAINTAINERS: Add Hyper-V IOMMU driver into Hyper-V CORE AND DRIVERS scope
  iommu/hyper-v: Add Hyper-V stub IOMMU driver
  x86/Hyper-V: Set x2apic destination mode to physical when x2apic is available
  PCI/ATS: Add inline to pci_prg_resp_pasid_required()
  iommu/vt-d: Check identity map for hot-added devices
  iommu: Fix IOMMU debugfs fallout
  iommu: Document iommu_ops.is_attach_deferred()
  iommu: Document iommu_ops.iotlb_sync_map()
  iommu/vt-d: Enable ATS only if the device uses page aligned address.
  PCI/ATS: Add pci_ats_page_aligned() interface
  iommu/vt-d: Fix PRI/PASID dependency issue.
  PCI/ATS: Add pci_prg_resp_pasid_required() interface.
  iommu/vt-d: Allow interrupts from the entire bus for aliased devices
  iommu/vt-d: Add helper to set an IRTE to verify only the bus number
  iommu: Fix flush_tlb_all typo
  ...
parents b7a7d1c1 d05e4c86

Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt

deleted100644 → 0
+0 −14
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NVIDIA Tegra 20 GART



Required properties:

- compatible: "nvidia,tegra20-gart"

- reg: Two pairs of cells specifying the physical address and size of

  the memory controller registers and the GART aperture respectively.



Example:



	gart {

		compatible = "nvidia,tegra20-gart";

		reg = <0x7000f024 0x00000018	/* controller registers */

		       0x58000000 0x02000000>;	/* GART aperture */

	};

Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt

+19 −8
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NVIDIA Tegra20 MC(Memory Controller)



Required properties:

- compatible : "nvidia,tegra20-mc"

- reg : Should contain 2 register ranges(address and length); see the

  example below. Note that the MC registers are interleaved with the

  GART registers, and hence must be represented as multiple ranges.

- compatible : "nvidia,tegra20-mc-gart"

- reg : Should contain 2 register ranges: physical base address and length of

  the controller's registers and the GART aperture respectively.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - mc: the module's clock input

- interrupts : Should contain MC General interrupt.

- #reset-cells : Should be 1. This cell represents memory client module ID.

  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>

  or in the TRM documentation.

- #iommu-cells: Should be 0. This cell represents the number of cells in an

  IOMMU specifier needed to encode an address. GART supports only a single

  address space that is shared by all devices, therefore no additional

  information needed for the address encoding.



Example:

	mc: memory-controller@7000f000 {

		compatible = "nvidia,tegra20-mc";

		reg = <0x7000f000 0x024

		       0x7000f03c 0x3c4>;

		interrupts = <0 77 0x04>;

		compatible = "nvidia,tegra20-mc-gart";

		reg = <0x7000f000 0x400		/* controller registers */

		       0x58000000 0x02000000>;	/* GART aperture */

		clocks = <&tegra_car TEGRA20_CLK_MC>;

		clock-names = "mc";

		interrupts = <GIC_SPI 77 0x04>;

		#reset-cells = <1>;

		#iommu-cells = <0>;

	};



	video-codec@6001a000 {

		compatible = "nvidia,tegra20-vde";

		...

		resets = <&mc TEGRA20_MC_RESET_VDE>;

		iommus = <&mc>;

	};

MAINTAINERS

+1 −0
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@@ -7170,6 +7170,7 @@ F: drivers/net/hyperv/ 
F:	drivers/scsi/storvsc_drv.c

F:	drivers/uio/uio_hv_generic.c

F:	drivers/video/fbdev/hyperv_fb.c

F:	drivers/iommu/hyperv_iommu.c

F:	net/vmw_vsock/hyperv_transport.c

F:	include/linux/hyperv.h

F:	include/uapi/linux/hyperv.h

arch/arm/boot/dts/tegra20.dtsi

+6 −9
Original line number Diff line number Diff line
@@ -616,17 +616,14 @@ 
	};



	mc: memory-controller@7000f000 {

		compatible = "nvidia,tegra20-mc";

		reg = <0x7000f000 0x024

		       0x7000f03c 0x3c4>;

		compatible = "nvidia,tegra20-mc-gart";

		reg = <0x7000f000 0x400		/* controller registers */

		       0x58000000 0x02000000>;	/* GART aperture */

		clocks = <&tegra_car TEGRA20_CLK_MC>;

		clock-names = "mc";

		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

		#reset-cells = <1>;

	};



	iommu@7000f024 {

		compatible = "nvidia,tegra20-gart";

		reg = <0x7000f024 0x00000018	/* controller registers */

		       0x58000000 0x02000000>;	/* GART aperture */

		#iommu-cells = <0>;

	};



	memory-controller@7000f400 {

arch/x86/kernel/cpu/mshyperv.c

+12 −0
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@@ -328,6 +328,18 @@ static void __init ms_hyperv_init_platform(void) 
# ifdef CONFIG_SMP

	smp_ops.smp_prepare_boot_cpu = hv_smp_prepare_boot_cpu;

# endif



	/*

	 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,

	 * set x2apic destination mode to physcial mode when x2apic is available

	 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs

	 * have 8-bit APIC id.

	 */

# ifdef CONFIG_X86_X2APIC

	if (x2apic_supported())

		x2apic_phys = 1;

# endif



#endif

}