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Commit bb5a3bd3 authored by Mukund Madhusudan Atre's avatar Mukund Madhusudan Atre
Browse files

ARM: dts: msm: Fix order of clock naming in csid lite node for lahaina 

The order of clock names should be same as the order of its clock
values. Fix order of name for ahb clock in csid lite device tree
node in camera.

CRs-Fixed: 2583813
Change-Id: I265af8f302ac4d857f479d3ddd556bae13f872db
parent 7fc312b7

lahaina-camera.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -819,7 +819,7 @@ 
					<CAM_CPAS_TRANSACTION_WRITE>;

					constituent-paths =

					<CAM_CPAS_PATH_DATA_IFE_LINEAR

					CAM_CPAS_PATH_DATA_IFE_PDAF>; // TODO

					CAM_CPAS_PATH_DATA_IFE_PDAF>;

					parent-node = <&level1_rt0_wr1>;

				};
@@ -833,7 +833,7 @@ 
					<CAM_CPAS_TRANSACTION_WRITE>;

					constituent-paths =

					<CAM_CPAS_PATH_DATA_IFE_LINEAR

					CAM_CPAS_PATH_DATA_IFE_PDAF>; // TODO

					CAM_CPAS_PATH_DATA_IFE_PDAF>;

					parent-node = <&level1_rt0_wr1>;

				};
@@ -1506,11 +1506,11 @@ 
		camss-supply = <&cam_cc_titan_top_gdsc>;

		clock-names =

			"ife_csid_clk_src",

			"ife_lite_ahb",

			"ife_csid_clk",

			"cphy_rx_clk_src",

			"ife_cphy_rx_clk",

			"ife_clk_src",

			"ife_lite_ahb",

			"ife_clk";

		clocks =

			<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,