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Commit baf585e2 authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Merge 0b595d4f on remote branch 

Change-Id: Ide4872ae0dcb8f469f7c139e972d2fe7b3caf929
parents e3dea79a 0b595d4f

msm/dp/dp_power.c

+11 −9
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.

 */



#include <linux/clk.h>
@@ -212,21 +212,23 @@ static int dp_power_clk_init(struct dp_power_private *power, bool enable) 


		power->pixel_parent = clk_get(dev, "pixel_parent");

		if (IS_ERR(power->pixel_parent)) {

			DP_DEBUG("Unable to get DP pixel RCG parent: %d\n",

			DP_ERR("Unable to get DP pixel RCG parent: %d\n",

					PTR_ERR(power->pixel_parent));

			rc = PTR_ERR(power->pixel_parent);

			power->pixel_parent = NULL;

			goto err_pixel_parent;

		}



		if (power->parser->has_mst) {

			power->pixel1_clk_rcg = clk_get(dev, "pixel1_clk_rcg");

			if (IS_ERR(power->pixel1_clk_rcg)) {

			DP_DEBUG("Unable to get DP pixel1 clk RCG: %d\n",

				DP_ERR("Unable to get DP pixel1 clk RCG: %d\n",

						PTR_ERR(power->pixel1_clk_rcg));

				rc = PTR_ERR(power->pixel1_clk_rcg);

				power->pixel1_clk_rcg = NULL;

				goto err_pixel1_clk_rcg;

			}

		}

	} else {

		if (power->pixel1_clk_rcg)

			clk_put(power->pixel1_clk_rcg);

msm/dsi/dsi_display.c

+14 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.

 */



#include <linux/list.h>
@@ -4625,7 +4625,6 @@ static int _dsi_display_dyn_update_clks(struct dsi_display *display, 
		dsi_phy_dynamic_refresh_clear(ctrl->phy);

	}



defer_dfps_wait:

	rc = dsi_clk_update_parent(enable_clk,

			&display->clock_info.mux_clks);

	if (rc)
@@ -4657,9 +4656,22 @@ static int _dsi_display_dyn_update_clks(struct dsi_display *display, 
exit:

	dsi_clk_disable_unprepare(&display->clock_info.src_clks);



defer_dfps_wait:

	return rc;

}



void dsi_display_dfps_update_parent(struct dsi_display *display)

{

	int rc = 0;



	rc = dsi_clk_update_parent(&display->clock_info.src_clks,

			      &display->clock_info.mux_clks);

	if (rc)

		DSI_ERR("could not switch back to src clks %d\n", rc);



	dsi_clk_disable_unprepare(&display->clock_info.src_clks);

}



static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display,

					  struct dsi_display_mode *mode)

{

msm/dsi/dsi_display.h

+7 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.

 */



#ifndef _DSI_DISPLAY_H_
@@ -785,4 +785,10 @@ int dsi_display_get_panel_vfp(void *display, 
 */

int dsi_display_dump_clks_state(struct dsi_display *display);



/**

 * dsi_display_dfps_update_parent() - update dsi clock parent to src clock

 * @display:         Handle to display

 */

void dsi_display_dfps_update_parent(struct dsi_display *display);



#endif /* _DSI_DISPLAY_H_ */

msm/dsi/dsi_drm.c

+3 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.

 */
@@ -1065,6 +1065,8 @@ int dsi_conn_post_kickoff(struct drm_connector *connector, 
						ctrl->ctrl);

				if (rc)

					DSI_ERR("wait4dfps refresh failed\n");

				dsi_display_dfps_update_parent(display);

				dsi_phy_dynamic_refresh_clear(ctrl->phy);

			}

		}

msm/sde/sde_hw_catalog.c

+0 −1
Original line number Diff line number Diff line
@@ -4825,7 +4825,6 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		set_bit(SDE_MDP_DHDR_MEMPOOL_4K, &sde_cfg->mdp[0].features);

		sde_cfg->has_vig_p010 = true;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_0;

		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_1;

		sde_cfg->vbif_disable_inner_outer_shareable = true;

		sde_cfg->dither_luma_mode_support = true;

		sde_cfg->mdss_hw_block_size = 0x158;