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Commit bae120f8 authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

arm64: uniphier: dts: add more clocks to Denali NAND controller node 



Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.

For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 007a9389

arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -571,7 +571,8 @@ 
			interrupts = <0 65 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_nand>;

			clocks = <&sys_clk 2>;

			clock-names = "nand", "nand_x", "ecc";

			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;

			resets = <&sys_rst 2>;

		};

	};

arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -628,7 +628,8 @@ 
			interrupts = <0 65 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_nand>;

			clocks = <&sys_clk 2>;

			clock-names = "nand", "nand_x", "ecc";

			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;

			resets = <&sys_rst 2>;

		};

	};

arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -455,7 +455,8 @@ 
			interrupts = <0 65 4>;

			pinctrl-names = "default";

			pinctrl-0 = <&pinctrl_nand>;

			clocks = <&sys_clk 2>;

			clock-names = "nand", "nand_x", "ecc";

			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;

			resets = <&sys_rst 2>;

		};

	};