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Commit bae04655 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add QUPv3 DT nodes for shima trusted VM"

parents 6416746e 44bc9c82

qcom/shima-qupv3.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -53,7 +53,8 @@ 
			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;

		qcom,gpii-mask = <0xff>;

		qcom,static-gpii-mask = <0x1>;

		qcom,gpii-mask = <0x7e>;

		qcom,ev-factor = <2>;

		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;

		qcom,gpi-ee-offset = <0x10000>;
@@ -174,8 +175,8 @@ 
		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se10_i2c_active>;

		pinctrl-1 = <&qupv3_se10_i2c_sleep>;

		dmas = <&gpi_dma0 0 2 3 64 0>,

			<&gpi_dma0 1 2 3 64 0>;

		dmas = <&gpi_dma0 0 2 3 64 2>,

			<&gpi_dma0 1 2 3 64 2>;

		dma-names = "tx", "rx";

		qcom,wrapper-core = <&qupv3_0>;

		status = "disabled";

qcom/shima-vm.dtsi

+51 −0
Original line number Diff line number Diff line
@@ -224,5 +224,56 @@ 
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

	};



	/*

	 * QUPv3 Instances

	 * Qup0 2: SE 10

	 */



	/* QUPv3_0 wrapper instance */

	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x9c0000 0x2000>;

	};



	/* GPI Instance */

	gpi_dma0: qcom,gpi-dma@900000 {

		compatible = "qcom,gpi-dma";

		#dma-cells = <5>;

		reg = <0x900000 0x60000>;

		reg-names = "gpi-top";

		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;

		qcom,max-num-gpii = <12>;

		qcom,gpii-mask = <0x80>;

		qcom,ev-factor = <2>;

		qcom,gpi-ee-offset = <0x10000>;

		status = "ok";

	};



	/* I2C SE */

	qupv3_se10_i2c: i2c@988000 {

		compatible = "qcom,i2c-geni";

		reg = <0x988000 0x4000>;

		#address-cells = <1>;

		#size-cells = <0>;

		dmas = <&gpi_dma0 0 2 3 64 0>,

			<&gpi_dma0 1 2 3 64 0>;

		dma-names = "tx", "rx";

		qcom,wrapper-core = <&qupv3_0>;

		qcom,le-vm;

		status = "disabled";

	};



};

#include "lahaina-vm-ion.dtsi"