Loading drivers/gpu/msm/adreno_a6xx_gmu.c +9 −8 Original line number Diff line number Diff line Loading @@ -2192,6 +2192,15 @@ static int a6xx_gmu_first_boot(struct adreno_device *adreno_dev) goto err; } if (!test_bit(GMU_PRIV_PDC_RSC_LOADED, &gmu->flags)) { ret = a6xx_load_pdc_ucode(adreno_dev); if (ret) goto err; a6xx_load_rsc_ucode(adreno_dev); set_bit(GMU_PRIV_PDC_RSC_LOADED, &gmu->flags); } ret = a6xx_gmu_hfi_start(adreno_dev); if (ret) goto err; Loading Loading @@ -2988,14 +2997,6 @@ static int a6xx_first_boot(struct adreno_device *adreno_dev) if (ret) return ret; ret = a6xx_load_pdc_ucode(adreno_dev); if (ret) { a6xx_gmu_power_off(adreno_dev); return ret; } a6xx_load_rsc_ucode(adreno_dev); adreno_get_bus_counters(adreno_dev); adreno_dev->cooperative_reset = ADRENO_FEATURE(adreno_dev, Loading drivers/gpu/msm/adreno_a6xx_gmu.h +1 −0 Original line number Diff line number Diff line Loading @@ -137,6 +137,7 @@ enum { GMU_PRIV_HFI_STARTED, GMU_PRIV_RSCC_SLEEP_DONE, GMU_PRIV_PM_SUSPEND, GMU_PRIV_PDC_RSC_LOADED, }; /** Loading Loading
drivers/gpu/msm/adreno_a6xx_gmu.c +9 −8 Original line number Diff line number Diff line Loading @@ -2192,6 +2192,15 @@ static int a6xx_gmu_first_boot(struct adreno_device *adreno_dev) goto err; } if (!test_bit(GMU_PRIV_PDC_RSC_LOADED, &gmu->flags)) { ret = a6xx_load_pdc_ucode(adreno_dev); if (ret) goto err; a6xx_load_rsc_ucode(adreno_dev); set_bit(GMU_PRIV_PDC_RSC_LOADED, &gmu->flags); } ret = a6xx_gmu_hfi_start(adreno_dev); if (ret) goto err; Loading Loading @@ -2988,14 +2997,6 @@ static int a6xx_first_boot(struct adreno_device *adreno_dev) if (ret) return ret; ret = a6xx_load_pdc_ucode(adreno_dev); if (ret) { a6xx_gmu_power_off(adreno_dev); return ret; } a6xx_load_rsc_ucode(adreno_dev); adreno_get_bus_counters(adreno_dev); adreno_dev->cooperative_reset = ADRENO_FEATURE(adreno_dev, Loading
drivers/gpu/msm/adreno_a6xx_gmu.h +1 −0 Original line number Diff line number Diff line Loading @@ -137,6 +137,7 @@ enum { GMU_PRIV_HFI_STARTED, GMU_PRIV_RSCC_SLEEP_DONE, GMU_PRIV_PM_SUSPEND, GMU_PRIV_PDC_RSC_LOADED, }; /** Loading