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Commit b9e111aa authored by Sudheer Papothi's avatar Sudheer Papothi Committed by Gerrit - the friendly Code Review server
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ASoC: bolero: Update regmap to configure tx path 



Update regmap table with proper read write registers to
enable tx paths in a three mic usecase.

Change-Id: Iab53e3a92f02ddc282e621b8063f3c051fe658f6
Signed-off-by: default avatarSudheer Papothi <spapothi@codeaurora.org>
parent 68f58b0d

asoc/codecs/bolero/bolero-cdc-tables.c

+4 −0
Original line number Diff line number Diff line
@@ -750,6 +750,10 @@ u8 bolero_va_reg_access_v3[BOLERO_CDC_VA_MACRO_MAX] = { 
	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG1)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG0)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG1)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG0)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG1)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG0)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG1)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CTL)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CFG0)] = RD_WR_REG,

	[BOLERO_REG(BOLERO_CDC_VA_TX0_TX_PATH_CFG1)] = RD_WR_REG,

asoc/codecs/bolero/va-macro.c

+2 −0
Original line number Diff line number Diff line
@@ -2419,6 +2419,8 @@ static const struct snd_kcontrol_new va_macro_snd_controls_v3[] = { 
	SOC_SINGLE_SX_TLV("VA_DEC3 Volume",

			  BOLERO_CDC_VA_TX3_TX_VOL_CTL,

			  0, -84, 40, digital_gain),

	SOC_SINGLE_EXT("LPI Enable", 0, 0, 1, 0,

		va_macro_lpi_get, va_macro_lpi_put),

};



static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,