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Commit b9be7853 authored by José Roberto de Souza's avatar José Roberto de Souza Committed by Rodrigo Vivi
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drm/i915/whl: Introducing Whiskey Lake platform 



Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.

So, let's just move them to WHL macros that will feed into CFL macro
just to keep it better organized to make easier future code review
but it will be handled as a CFL.

v2:
Fixing GT level of some ids

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180614233720.30517-1-jose.souza@intel.com
parent 5ee4a7a6

drivers/gpu/drm/i915/i915_pci.c

+3 −1
Original line number Diff line number Diff line
@@ -660,9 +660,11 @@ static const struct pci_device_id pciidlist[] = { 
	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),

	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),

	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),

	INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),

	INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),

	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),

	INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info),

	INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),

	INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),

	INTEL_CNL_IDS(&intel_cannonlake_info),

	INTEL_ICL_11_IDS(&intel_icelake_11_info),

	{0, 0, 0}

include/drm/i915_pciids.h

+18 −10
Original line number Diff line number Diff line
@@ -388,32 +388,40 @@ 
	INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \

	INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */



/* CFL U GT1 */

#define INTEL_CFL_U_GT1_IDS(info) \

	INTEL_VGA_DEVICE(0x3EA1, info), \

	INTEL_VGA_DEVICE(0x3EA4, info)



/* CFL U GT2 */

#define INTEL_CFL_U_GT2_IDS(info) \

	INTEL_VGA_DEVICE(0x3EA0, info), \

	INTEL_VGA_DEVICE(0x3EA3, info), \

	INTEL_VGA_DEVICE(0x3EA9, info)



/* CFL U GT3 */

#define INTEL_CFL_U_GT3_IDS(info) \

	INTEL_VGA_DEVICE(0x3EA2, info), /* ULT GT3 */ \

	INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \

	INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \

	INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \

	INTEL_VGA_DEVICE(0x3EA8, info)  /* ULT GT3 */



/* WHL/CFL U GT1 */

#define INTEL_WHL_U_GT1_IDS(info) \

	INTEL_VGA_DEVICE(0x3EA1, info)



/* WHL/CFL U GT2 */

#define INTEL_WHL_U_GT2_IDS(info) \

	INTEL_VGA_DEVICE(0x3EA0, info)



/* WHL/CFL U GT3 */

#define INTEL_WHL_U_GT3_IDS(info) \

	INTEL_VGA_DEVICE(0x3EA2, info), \

	INTEL_VGA_DEVICE(0x3EA3, info), \

	INTEL_VGA_DEVICE(0x3EA4, info)



#define INTEL_CFL_IDS(info)	   \

	INTEL_CFL_S_GT1_IDS(info), \

	INTEL_CFL_S_GT2_IDS(info), \

	INTEL_CFL_H_GT2_IDS(info), \

	INTEL_CFL_U_GT1_IDS(info), \

	INTEL_CFL_U_GT2_IDS(info), \

	INTEL_CFL_U_GT3_IDS(info)

	INTEL_CFL_U_GT3_IDS(info), \

	INTEL_WHL_U_GT1_IDS(info), \

	INTEL_WHL_U_GT2_IDS(info), \

	INTEL_WHL_U_GT3_IDS(info)



/* CNL */

#define INTEL_CNL_IDS(info) \