Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b99bb4d2 authored by Saurabh Sahu's avatar Saurabh Sahu
Browse files

clk: qcom: alpha-pll: define common macros for PLL 



Update the lucid_5lpe zonda_5lpe lucid_evo zonda_evo pll
ENABLE_VOTE_RUN macro to common ENABLE_VOTE_RUN macro.

Change-Id: I0f6db9acb9e89ef6e21c1d65179562af25b7b7fe
Signed-off-by: default avatarSaurabh Sahu <sausah@codeaurora.org>
parent f194a65c

drivers/clk/qcom/clk-alpha-pll.c

+11 −12
Original line number Diff line number Diff line
@@ -250,16 +250,16 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 
#define PLL_OPMODE_RUN		0x1

#define PLL_OUT_MASK		0x7

#define PLL_OUT_RATE_MARGIN	500

#define PLL_5LPE_ENABLE_VOTE_RUN	BIT(21)

#define PLL_EVO_ENABLE_VOTE_RUN		BIT(25)



/* LUCID PLL specific settings and offsets */

#define LUCID_PLL_CAL_VAL		0x44

#define LUCID_PCAL_DONE		BIT(27)

#define LUCID_5LPE_PCAL_DONE		BIT(11)

#define LUCID_5LPE_ENABLE_VOTE_RUN	BIT(21)

#define LUCID_5LPE_PLL_LATCH_INPUT	BIT(14)

#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH	BIT(13)

#define LUCID_EVO_PCAL_NOT_DONE		BIT(8)

#define LUCID_EVO_ENABLE_VOTE_RUN	BIT(25)

#define LUCID_EVO_PLL_L_VAL_MASK	GENMASK(15, 0)

#define LUCID_EVO_PLL_CAL_L_VAL_MASK	GENMASK(31, 16)
@@ -267,7 +267,6 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 
#define ZONDA_PLL_OUT_MASK		0xF

#define ZONDA_STAY_IN_CFA		BIT(16)

#define ZONDA_PLL_FREQ_LOCK_DET	BIT(29)

#define ZONDA_5LPE_ENABLE_VOTE_RUN	BIT(21)



/* FABIA PLL specific settings */

#define FABIA_PLL_CAL_VAL		0x3F
@@ -1644,7 +1643,7 @@ static int clk_zonda_5lpe_pll_enable(struct clk_hw *hw) 
		return ret;



	/* If in FSM mode, just vote for it */

	if (val & ZONDA_5LPE_ENABLE_VOTE_RUN) {

	if (val & PLL_5LPE_ENABLE_VOTE_RUN) {

		ret = clk_enable_regmap(hw);

		if (ret)

			return ret;
@@ -1711,7 +1710,7 @@ static void clk_zonda_5lpe_pll_disable(struct clk_hw *hw) 
		return;



	/* If in FSM mode, just unvote it */

	if (val & ZONDA_5LPE_ENABLE_VOTE_RUN) {

	if (val & PLL_5LPE_ENABLE_VOTE_RUN) {

		clk_disable_regmap(hw);

		return;

	}
@@ -2983,7 +2982,7 @@ static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw) 
		return ret;



	/* If in FSM mode, just vote for it */

	if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {

	if (val & PLL_5LPE_ENABLE_VOTE_RUN) {

		ret = clk_enable_regmap(hw);

		if (ret)

			return ret;
@@ -3040,7 +3039,7 @@ static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw) 
		return;



	/* If in FSM mode, just unvote it */

	if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {

	if (val & PLL_5LPE_ENABLE_VOTE_RUN) {

		clk_disable_regmap(hw);

		return;

	}
@@ -3189,7 +3188,7 @@ static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, 
	if (ret)

		return ret;



	if (val & LUCID_5LPE_ENABLE_VOTE_RUN)

	if (val & PLL_5LPE_ENABLE_VOTE_RUN)

		return 0;



	if (!pll->post_div_table) {
@@ -3450,7 +3449,7 @@ static int alpha_pll_lucid_evo_enable(struct clk_hw *hw) 
		return ret;



	/* If in FSM mode, just vote for it */

	if (val & LUCID_EVO_ENABLE_VOTE_RUN) {

	if (val & PLL_EVO_ENABLE_VOTE_RUN) {

		ret = clk_enable_regmap(hw);

		if (ret)

			return ret;
@@ -3507,7 +3506,7 @@ static void alpha_pll_lucid_evo_disable(struct clk_hw *hw) 
		return;



	/* If in FSM mode, just unvote it */

	if (val & LUCID_EVO_ENABLE_VOTE_RUN) {

	if (val & PLL_EVO_ENABLE_VOTE_RUN) {

		clk_disable_regmap(hw);

		return;

	}
@@ -3617,7 +3616,7 @@ static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, 
	if (ret)

		return ret;



	if (val & LUCID_EVO_ENABLE_VOTE_RUN)

	if (val & PLL_EVO_ENABLE_VOTE_RUN)

		return 0;



	if (!pll->post_div_table) {
@@ -3729,7 +3728,7 @@ static void lucid_evo_pll_list_registers(struct seq_file *f, 


	regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);



	if (val & LUCID_EVO_ENABLE_VOTE_RUN) {

	if (val & PLL_EVO_ENABLE_VOTE_RUN) {

		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +

					data1[0].offset, &val);

		clock_debug_output(f, "%20s: 0x%.8x\n", data1[0].name, val);