Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git (b9824cb8) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/net/wireless/ath/ath10k/core.c

+13 −0

Original line number	Diff line number	Diff line
		@@ -198,6 +198,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.name = "qca9984/qca9994 hw1.0",
		.patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
		.uart_pin = 7,
		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
		.otp_exe_param = 0x00000700,
		.continuous_frag_desc = true,
		.cck_rate_map_rev2 = true,
		@@ -223,6 +224,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
		.name = "qca9888 hw2.0",
		.patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
		.uart_pin = 7,
		.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
		.otp_exe_param = 0x00000700,
		.continuous_frag_desc = true,
		.channel_counters_freq_hz = 150000,
		@@ -1560,6 +1562,15 @@ static void ath10k_core_restart(struct work_struct *work)
		mutex_unlock(&ar->conf_mutex);
		}

		static void ath10k_core_set_coverage_class_work(struct work_struct *work)
		{
		struct ath10k *ar = container_of(work, struct ath10k,
		set_coverage_class_work);

		if (ar->hw_params.hw_ops->set_coverage_class)
		ar->hw_params.hw_ops->set_coverage_class(ar, -1);
		}

		static int ath10k_core_init_firmware_features(struct ath10k *ar)
		{
		struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
		@@ -2342,6 +2353,8 @@ struct ath10k ath10k_core_create(size_t priv_size, struct device dev,

		INIT_WORK(&ar->register_work, ath10k_core_register_work);
		INIT_WORK(&ar->restart_work, ath10k_core_restart);
		INIT_WORK(&ar->set_coverage_class_work,
		ath10k_core_set_coverage_class_work);

		init_dummy_netdev(&ar->napi_dev);

drivers/net/wireless/ath/ath10k/core.h

+14 −0

Original line number	Diff line number	Diff line
		@@ -713,6 +713,7 @@ struct ath10k {
		u32 phy_capability;
		u32 hw_min_tx_power;
		u32 hw_max_tx_power;
		u32 hw_eeprom_rd;
		u32 ht_cap_info;
		u32 vht_cap_info;
		u32 num_rf_chains;
		@@ -911,6 +912,19 @@ struct ath10k {
		struct net_device napi_dev;
		struct napi_struct napi;

		struct work_struct set_coverage_class_work;
		/* protected by conf_mutex */
		struct {
		/* writing also protected by data_lock */
		s16 coverage_class;

		u32 reg_phyclk;
		u32 reg_slottime_conf;
		u32 reg_slottime_orig;
		u32 reg_ack_cts_timeout_conf;
		u32 reg_ack_cts_timeout_orig;
		} fw_coverage;

		/* must be last */
		u8 drv_priv[0] __aligned(sizeof(void *));
		};

drivers/net/wireless/ath/ath10k/debug.h

+22 −0

Original line number	Diff line number	Diff line
		@@ -94,7 +94,19 @@ int ath10k_debug_get_et_sset_count(struct ieee80211_hw *hw,
		void ath10k_debug_get_et_stats(struct ieee80211_hw *hw,
		struct ieee80211_vif *vif,
		struct ethtool_stats stats, u64 data);

		static inline u64 ath10k_debug_get_fw_dbglog_mask(struct ath10k *ar)
		{
		return ar->debug.fw_dbglog_mask;
		}

		static inline u32 ath10k_debug_get_fw_dbglog_level(struct ath10k *ar)
		{
		return ar->debug.fw_dbglog_level;
		}

		#else

		static inline int ath10k_debug_start(struct ath10k *ar)
		{
		return 0;
		@@ -144,6 +156,16 @@ ath10k_debug_get_new_fw_crash_data(struct ath10k *ar)
		return NULL;
		}

		static inline u64 ath10k_debug_get_fw_dbglog_mask(struct ath10k *ar)
		{
		return 0;
		}

		static inline u32 ath10k_debug_get_fw_dbglog_level(struct ath10k *ar)
		{
		return 0;
		}

		#define ATH10K_DFS_STAT_INC(ar, c) do { } while (0)

		#define ath10k_debug_get_et_strings NULL

drivers/net/wireless/ath/ath10k/htt_rx.c

+6 −6

Original line number	Diff line number	Diff line
		@@ -1463,8 +1463,7 @@ static int ath10k_unchain_msdu(struct sk_buff_head *amsdu)
		}

		static void ath10k_htt_rx_h_unchain(struct ath10k *ar,
		struct sk_buff_head *amsdu,
		bool chained)
		struct sk_buff_head *amsdu)
		{
		struct sk_buff *first;
		struct htt_rx_desc *rxd;
		@@ -1475,9 +1474,6 @@ static void ath10k_htt_rx_h_unchain(struct ath10k *ar,
		decap = MS(__le32_to_cpu(rxd->msdu_start.common.info1),
		RX_MSDU_START_INFO1_DECAP_FORMAT);

		if (!chained)
		return;

		/* FIXME: Current unchaining logic can only handle simple case of raw
		* msdu chaining. If decapping is other than raw the chaining may be
		* more complex and this isn't handled by the current code. Don't even
		@@ -1555,7 +1551,11 @@ static int ath10k_htt_rx_handle_amsdu(struct ath10k_htt *htt)

		num_msdus = skb_queue_len(&amsdu);
		ath10k_htt_rx_h_ppdu(ar, &amsdu, rx_status, 0xffff);
		ath10k_htt_rx_h_unchain(ar, &amsdu, ret > 0);

		/* only for ret = 1 indicates chained msdus */
		if (ret > 0)
		ath10k_htt_rx_h_unchain(ar, &amsdu);

		ath10k_htt_rx_h_filter(ar, &amsdu, rx_status);
		ath10k_htt_rx_h_mpdu(ar, &amsdu, rx_status);
		ath10k_htt_rx_h_deliver(ar, &amsdu, rx_status);

drivers/net/wireless/ath/ath10k/hw.c

+142 −0

Original line number	Diff line number	Diff line
		@@ -17,11 +17,14 @@
		#include <linux/types.h>
		#include "core.h"
		#include "hw.h"
		#include "hif.h"
		#include "wmi-ops.h"

		const struct ath10k_hw_regs qca988x_regs = {
		.rtc_soc_base_address = 0x00004000,
		.rtc_wmac_base_address = 0x00005000,
		.soc_core_base_address = 0x00009000,
		.wlan_mac_base_address = 0x00020000,
		.ce_wrapper_base_address = 0x00057000,
		.ce0_base_address = 0x00057400,
		.ce1_base_address = 0x00057800,
		@@ -48,6 +51,7 @@ const struct ath10k_hw_regs qca6174_regs = {
		.rtc_soc_base_address = 0x00000800,
		.rtc_wmac_base_address = 0x00001000,
		.soc_core_base_address = 0x0003a000,
		.wlan_mac_base_address = 0x00020000,
		.ce_wrapper_base_address = 0x00034000,
		.ce0_base_address = 0x00034400,
		.ce1_base_address = 0x00034800,
		@@ -74,6 +78,7 @@ const struct ath10k_hw_regs qca99x0_regs = {
		.rtc_soc_base_address = 0x00080000,
		.rtc_wmac_base_address = 0x00000000,
		.soc_core_base_address = 0x00082000,
		.wlan_mac_base_address = 0x00030000,
		.ce_wrapper_base_address = 0x0004d000,
		.ce0_base_address = 0x0004a000,
		.ce1_base_address = 0x0004a400,
		@@ -109,6 +114,7 @@ const struct ath10k_hw_regs qca99x0_regs = {
		const struct ath10k_hw_regs qca4019_regs = {
		.rtc_soc_base_address = 0x00080000,
		.soc_core_base_address = 0x00082000,
		.wlan_mac_base_address = 0x00030000,
		.ce_wrapper_base_address = 0x0004d000,
		.ce0_base_address = 0x0004a000,
		.ce1_base_address = 0x0004a400,
		@@ -220,7 +226,143 @@ void ath10k_hw_fill_survey_time(struct ath10k ar, struct survey_info survey,
		survey->time_busy = CCNT_TO_MSEC(ar, rcc);
		}

		/* The firmware does not support setting the coverage class. Instead this
		* function monitors and modifies the corresponding MAC registers.
		*/
		static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,
		s16 value)
		{
		u32 slottime_reg;
		u32 slottime;
		u32 timeout_reg;
		u32 ack_timeout;
		u32 cts_timeout;
		u32 phyclk_reg;
		u32 phyclk;
		u64 fw_dbglog_mask;
		u32 fw_dbglog_level;

		mutex_lock(&ar->conf_mutex);

		/* Only modify registers if the core is started. */
		if ((ar->state != ATH10K_STATE_ON) &&
		(ar->state != ATH10K_STATE_RESTARTED))
		goto unlock;

		/* Retrieve the current values of the two registers that need to be
		* adjusted.
		*/
		slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
		WAVE1_PCU_GBL_IFS_SLOT);
		timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
		WAVE1_PCU_ACK_CTS_TIMEOUT);
		phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
		WAVE1_PHYCLK);
		phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1;

		if (value < 0)
		value = ar->fw_coverage.coverage_class;

		/* Break out if the coverage class and registers have the expected
		* value.
		*/
		if (value == ar->fw_coverage.coverage_class &&
		slottime_reg == ar->fw_coverage.reg_slottime_conf &&
		timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&
		phyclk_reg == ar->fw_coverage.reg_phyclk)
		goto unlock;

		/* Store new initial register values from the firmware. */
		if (slottime_reg != ar->fw_coverage.reg_slottime_conf)
		ar->fw_coverage.reg_slottime_orig = slottime_reg;
		if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)
		ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;
		ar->fw_coverage.reg_phyclk = phyclk_reg;

		/* Calculat new value based on the (original) firmware calculation. */
		slottime_reg = ar->fw_coverage.reg_slottime_orig;
		timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;

		/* Do some sanity checks on the slottime register. */
		if (slottime_reg % phyclk) {
		ath10k_warn(ar,
		"failed to set coverage class: expected integer microsecond value in register\n");

		goto store_regs;
		}

		slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
		slottime = slottime / phyclk;
		if (slottime != 9 && slottime != 20) {
		ath10k_warn(ar,
		"failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",
		slottime);

		goto store_regs;
		}

		/* Recalculate the register values by adding the additional propagation
		* delay (3us per coverage class).
		*/

		slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
		slottime += value * 3 * phyclk;
		slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX);
		slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT);
		slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) \| slottime;

		/* Update ack timeout (lower halfword). */
		ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
		ack_timeout += 3 * value * phyclk;
		ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
		ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);

		/* Update cts timeout (upper halfword). */
		cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
		cts_timeout += 3 * value * phyclk;
		cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
		cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);

		timeout_reg = ack_timeout \| cts_timeout;

		ath10k_hif_write32(ar,
		WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT,
		slottime_reg);
		ath10k_hif_write32(ar,
		WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT,
		timeout_reg);

		/* Ensure we have a debug level of WARN set for the case that the
		* coverage class is larger than 0. This is important as we need to
		* set the registers again if the firmware does an internal reset and
		* this way we will be notified of the event.
		*/
		fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar);
		fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar);

		if (value > 0) {
		if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN)
		fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN;
		fw_dbglog_mask = ~0;
		}

		ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level);

		store_regs:
		/* After an error we will not retry setting the coverage class. */
		spin_lock_bh(&ar->data_lock);
		ar->fw_coverage.coverage_class = value;
		spin_unlock_bh(&ar->data_lock);

		ar->fw_coverage.reg_slottime_conf = slottime_reg;
		ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;

		unlock:
		mutex_unlock(&ar->conf_mutex);
		}

		const struct ath10k_hw_ops qca988x_ops = {
		.set_coverage_class = ath10k_hw_qca988x_set_coverage_class,
		};

		static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)