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Commit b9541a89 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "pci: msm: Disable BDF halt for sdxlemur"

parents 631b5855 a508c150

drivers/pci/controller/pci-msm.c

+15 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ 
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL (0x174)

#define PCIE20_PARF_AXI_MSTR_RD_ADDR_HALT (0x1a4)

#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT (0x1a8)

#define PCIE20_PCIE_PARF_AXI_MSTR_WR_NS_BDF_HALT (0x4a0)

#define PCIE20_PARF_LTSSM (0x1b0)

#define PCIE20_PARF_INT_ALL_STATUS (0x224)

#define PCIE20_PARF_INT_ALL_CLEAR (0x228)
@@ -847,6 +848,7 @@ struct msm_pcie_dev_t { 
	bool linkdown_panic;

	uint32_t boot_option;

	bool pcie_halt_feature_dis;

	bool pcie_bdf_halt_dis;



	uint32_t rc_idx;

	uint32_t phy_ver;
@@ -1684,6 +1686,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->slv_addr_space_size);

	PCIE_DBG_FS(dev, "PCIe: halt_feature_dis is %d\n",

		dev->pcie_halt_feature_dis);

	PCIE_DBG_FS(dev, "PCIe: bdf_halt_dis is %d\n",

		dev->pcie_bdf_halt_dis);

	PCIE_DBG_FS(dev, "phy_status_offset: 0x%x\n",

		dev->phy_status_offset);

	PCIE_DBG_FS(dev, "phy_status_bit: %u\n",
@@ -4761,6 +4765,12 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev) 
				BIT(31) | val);

	}



	if (dev->pcie_bdf_halt_dis) {

		val = readl_relaxed(dev->parf + PCIE20_PCIE_PARF_AXI_MSTR_WR_NS_BDF_HALT);

		msm_pcie_write_reg(dev->parf, PCIE20_PCIE_PARF_AXI_MSTR_WR_NS_BDF_HALT,

				(~BIT(0)) & val);

	}



	/* init tcsr */

	if (dev->tcsr_config)

		pcie_tcsr_init(dev);
@@ -6312,6 +6322,11 @@ static int msm_pcie_probe(struct platform_device *pdev) 
	PCIE_DBG(pcie_dev, "PCIe halt feature is %s enabled.\n",

			pcie_dev->pcie_halt_feature_dis ? "not" : "");



	pcie_dev->pcie_bdf_halt_dis = of_property_read_bool(of_node,

			"qcom,bdf-halt-dis");

	PCIE_DBG(pcie_dev, "PCIe BDF halt feature is %s enabled.\n",

			pcie_dev->pcie_bdf_halt_dis ? "not" : "");



	of_property_read_u32(of_node, "qcom,phy-status-offset",

				&pcie_dev->phy_status_offset);

	PCIE_DBG(pcie_dev, "RC%d: phy-status-offset: 0x%x.\n", pcie_dev->rc_idx,