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Commit b92b415f authored by Evan Quan's avatar Evan Quan Committed by Greg Kroah-Hartman
Browse files

drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading 



[ Upstream commit 2c5b8080d810d98e3e59617680218499b17c84a1 ]

The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 73a0e628

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

+0 −6
Original line number Diff line number Diff line
@@ -1640,12 +1640,6 @@ static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr) 


	data->uvd_power_gated = true;

	data->vce_power_gated = true;



	if (data->smu_features[GNLD_DPM_UVD].enabled)

		data->uvd_power_gated = false;



	if (data->smu_features[GNLD_DPM_VCE].enabled)

		data->vce_power_gated = false;

}



static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)