Loading drivers/clk/qcom/clk-alpha-pll.c +24 −18 Original line number Diff line number Diff line Loading @@ -272,6 +272,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define LUCID_5LPE_PCAL_DONE BIT(11) #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) #define LUCID_5LPE_BYPASS_LATCH BIT(10) #define LUCID_EVO_PCAL_NOT_DONE BIT(8) #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) #define LUCID_EVO_PLL_CAL_L_VAL_MASK GENMASK(31, 16) Loading Loading @@ -3171,6 +3172,10 @@ static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); if (pll->flags & BYPASS_LATCH) { regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL_U(pll), LUCID_5LPE_BYPASS_LATCH, LUCID_5LPE_BYPASS_LATCH); } else { /* Latch the PLL input */ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), LUCID_5LPE_PLL_LATCH_INPUT, LUCID_5LPE_PLL_LATCH_INPUT); Loading @@ -3191,6 +3196,7 @@ static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, LUCID_5LPE_PLL_LATCH_INPUT, 0); if (ret) return ret; } if (clk_hw_is_enabled(hw)) { ret = wait_for_pll_enable_lock(pll); Loading drivers/clk/qcom/clk-alpha-pll.h +1 −0 Original line number Diff line number Diff line Loading @@ -94,6 +94,7 @@ struct clk_alpha_pll { #define SUPPORTS_DYNAMIC_UPDATE BIT(3) #define SUPPORTS_FSM_LEGACY_MODE BIT(4) #define SUPPORTS_SLEW BIT(4) #define BYPASS_LATCH BIT(6) u8 flags; struct clk_regmap clkr; Loading drivers/clk/qcom/clk-cpu-sdxlemur.c +2 −1 Original line number Diff line number Diff line Loading @@ -299,6 +299,7 @@ static struct clk_alpha_pll apcs_cpu_pll = { .vco_table = lucid_5lpe_vco, .num_vco = ARRAY_SIZE(lucid_5lpe_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_5LPE], .flags = BYPASS_LATCH, .clkr = { .hw.init = &(struct clk_init_data){ .name = "apcs_cpu_pll", Loading @@ -306,7 +307,7 @@ static struct clk_alpha_pll apcs_cpu_pll = { .fw_name = "bi_tcxo_ao", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_5lpe_sdx_cpu_ops, .ops = &clk_alpha_pll_lucid_5lpe_ops, }, .vdd_data = { .vdd_class = &vdd_pll, Loading Loading
drivers/clk/qcom/clk-alpha-pll.c +24 −18 Original line number Diff line number Diff line Loading @@ -272,6 +272,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define LUCID_5LPE_PCAL_DONE BIT(11) #define LUCID_5LPE_PLL_LATCH_INPUT BIT(14) #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13) #define LUCID_5LPE_BYPASS_LATCH BIT(10) #define LUCID_EVO_PCAL_NOT_DONE BIT(8) #define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0) #define LUCID_EVO_PLL_CAL_L_VAL_MASK GENMASK(31, 16) Loading Loading @@ -3171,6 +3172,10 @@ static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); if (pll->flags & BYPASS_LATCH) { regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL_U(pll), LUCID_5LPE_BYPASS_LATCH, LUCID_5LPE_BYPASS_LATCH); } else { /* Latch the PLL input */ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), LUCID_5LPE_PLL_LATCH_INPUT, LUCID_5LPE_PLL_LATCH_INPUT); Loading @@ -3191,6 +3196,7 @@ static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate, LUCID_5LPE_PLL_LATCH_INPUT, 0); if (ret) return ret; } if (clk_hw_is_enabled(hw)) { ret = wait_for_pll_enable_lock(pll); Loading
drivers/clk/qcom/clk-alpha-pll.h +1 −0 Original line number Diff line number Diff line Loading @@ -94,6 +94,7 @@ struct clk_alpha_pll { #define SUPPORTS_DYNAMIC_UPDATE BIT(3) #define SUPPORTS_FSM_LEGACY_MODE BIT(4) #define SUPPORTS_SLEW BIT(4) #define BYPASS_LATCH BIT(6) u8 flags; struct clk_regmap clkr; Loading
drivers/clk/qcom/clk-cpu-sdxlemur.c +2 −1 Original line number Diff line number Diff line Loading @@ -299,6 +299,7 @@ static struct clk_alpha_pll apcs_cpu_pll = { .vco_table = lucid_5lpe_vco, .num_vco = ARRAY_SIZE(lucid_5lpe_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_5LPE], .flags = BYPASS_LATCH, .clkr = { .hw.init = &(struct clk_init_data){ .name = "apcs_cpu_pll", Loading @@ -306,7 +307,7 @@ static struct clk_alpha_pll apcs_cpu_pll = { .fw_name = "bi_tcxo_ao", }, .num_parents = 1, .ops = &clk_alpha_pll_lucid_5lpe_sdx_cpu_ops, .ops = &clk_alpha_pll_lucid_5lpe_ops, }, .vdd_data = { .vdd_class = &vdd_pll, Loading
