Commit b915fac0 authored Nov 23, 2022 by Fabrice Gasnier Committed by Greg Kroah-Hartman Mar 11, 2023

pwm: stm32-lp: fix the check on arr and cmp registers update



[ Upstream commit 3066bc2d58be31275afb51a589668f265e419c37 ]

The ARR (auto reload register) and CMP (compare) registers are
successively written. The status bits to check the update of these
registers are polled together with regmap_read_poll_timeout().
The condition to end the loop may become true, even if one of the
register isn't correctly updated.
So ensure both status bits are set before clearing them.

Fixes: e70a540b ("pwm: Add STM32 LPTimer PWM driver")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent 1abd3858

drivers/pwm/pwm-stm32-lp.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -127,7 +127,7 @@ static int stm32_pwm_lp_apply(struct pwm_chip chip, struct pwm_device pwm,

		/* ensure CMP & ARR registers are properly written */
		ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
		(val & STM32_LPTIM_CMPOK_ARROK),
		(val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,
		100, 1000);
		if (ret) {
		dev_err(priv->chip.dev, "ARR/CMP registers write issue\n");