Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Unverified Commit b90edb33 authored by Jim Wilson's avatar Jim Wilson Committed by Palmer Dabbelt
Browse files

RISC-V: Add futex support. 

Here is an attempt to add the missing futex support.  I started with the MIPS
version of futex.h and modified it until I got it working.  I tested it on
a HiFive Unleashed running Fedora Core 29 using the fc29 4.15 version of the
kernel.  This was tested against the glibc testsuite, where it fixes 14 nptl
related testsuite failures.  That unfortunately only tests the cmpxchg support,
so I also used the testcase at the end of

    https://lwn.net/Articles/148830/



which tests the atomic_op functionality, except that it doesn't verify that
the operations are atomic, which they obviously are.  This testcase runs
successfully with the patch and fails without it.

I'm not a kernel expert, so there could be details I got wrong here.  I wasn't
sure about the memory model support, so I used aqrl which seemed safest, and
didn't add fences which seemed unnecessary.  I'm not sure about the copyright
statements, I left in Ralf Baechle's line because I started with his code.
Checkpatch reports some style problems, but it is the same style as the MIPS
futex.h, and the uses of ENOSYS appear correct even though it complains about
them.  I don't know if any of that matters.

This patch was tested on qemu with the glibc nptl/tst-cond-except
testcase, and the wake_op testcase from above.

Signed-off-by: default avatarJim Wilson <jimw@sifive.com>
Reviewed-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent b8c8a959

arch/riscv/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ config RISCV 
	select HAVE_MEMBLOCK

	select HAVE_MEMBLOCK_NODE_MAP

	select HAVE_DMA_CONTIGUOUS

	select HAVE_FUTEX_CMPXCHG if FUTEX

	select HAVE_GENERIC_DMA_COHERENT

	select HAVE_PERF_EVENTS

	select IRQ_DOMAIN

arch/riscv/include/asm/Kbuild

+0 −1
Original line number Diff line number Diff line
@@ -13,7 +13,6 @@ generic-y += errno.h 
generic-y += exec.h

generic-y += fb.h

generic-y += fcntl.h

generic-y += futex.h

generic-y += hardirq.h

generic-y += hash.h

generic-y += hw_irq.h

arch/riscv/include/asm/futex.h

0 → 100644
+128 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (c) 2006  Ralf Baechle (ralf@linux-mips.org)

 * Copyright (c) 2018  Jim Wilson (jimw@sifive.com)

 */



#ifndef _ASM_FUTEX_H

#define _ASM_FUTEX_H



#ifndef CONFIG_RISCV_ISA_A

/*

 * Use the generic interrupt disabling versions if the A extension

 * is not supported.

 */

#ifdef CONFIG_SMP

#error "Can't support generic futex calls without A extension on SMP"

#endif

#include <asm-generic/futex.h>



#else /* CONFIG_RISCV_ISA_A */



#include <linux/futex.h>

#include <linux/uaccess.h>

#include <linux/errno.h>

#include <asm/asm.h>



#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)	\

{								\

	uintptr_t tmp;						\

	__enable_user_access();					\

	__asm__ __volatile__ (					\

	"1:	" insn "				\n"	\

	"2:						\n"	\

	"	.section .fixup,\"ax\"			\n"	\

	"	.balign 4				\n"	\

	"3:	li %[r],%[e]				\n"	\

	"	jump 2b,%[t]				\n"	\

	"	.previous				\n"	\

	"	.section __ex_table,\"a\"		\n"	\

	"	.balign " RISCV_SZPTR "			\n"	\

	"	" RISCV_PTR " 1b, 3b			\n"	\

	"	.previous				\n"	\

	: [r] "+r" (ret), [ov] "=&r" (oldval),			\

	  [u] "+m" (*uaddr), [t] "=&r" (tmp)			\

	: [op] "Jr" (oparg), [e] "i" (-EFAULT)			\

	: "memory");						\

	__disable_user_access();				\

}



static inline int

arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)

{

	int oldval = 0, ret = 0;



	pagefault_disable();



	switch (op) {

	case FUTEX_OP_SET:

		__futex_atomic_op("amoswap.w.aqrl %[ov],%z[op],%[u]",

				  ret, oldval, uaddr, oparg);

		break;

	case FUTEX_OP_ADD:

		__futex_atomic_op("amoadd.w.aqrl %[ov],%z[op],%[u]",

				  ret, oldval, uaddr, oparg);

		break;

	case FUTEX_OP_OR:

		__futex_atomic_op("amoor.w.aqrl %[ov],%z[op],%[u]",

				  ret, oldval, uaddr, oparg);

		break;

	case FUTEX_OP_ANDN:

		__futex_atomic_op("amoand.w.aqrl %[ov],%z[op],%[u]",

				  ret, oldval, uaddr, ~oparg);

		break;

	case FUTEX_OP_XOR:

		__futex_atomic_op("amoxor.w.aqrl %[ov],%z[op],%[u]",

				  ret, oldval, uaddr, oparg);

		break;

	default:

		ret = -ENOSYS;

	}



	pagefault_enable();



	if (!ret)

		*oval = oldval;



	return ret;

}



static inline int

futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,

			      u32 oldval, u32 newval)

{

	int ret = 0;

	u32 val;

	uintptr_t tmp;



	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))

		return -EFAULT;



	__enable_user_access();

	__asm__ __volatile__ (

	"1:	lr.w.aqrl %[v],%[u]			\n"

	"	bne %[v],%z[ov],3f			\n"

	"2:	sc.w.aqrl %[t],%z[nv],%[u]		\n"

	"	bnez %[t],1b				\n"

	"3:						\n"

	"	.section .fixup,\"ax\"			\n"

	"	.balign 4				\n"

	"4:	li %[r],%[e]				\n"

	"	jump 3b,%[t]				\n"

	"	.previous				\n"

	"	.section __ex_table,\"a\"		\n"

	"	.balign " RISCV_SZPTR "			\n"

	"	" RISCV_PTR " 1b, 4b			\n"

	"	" RISCV_PTR " 2b, 4b			\n"

	"	.previous				\n"

	: [r] "+r" (ret), [v] "=&r" (val), [u] "+m" (*uaddr), [t] "=&r" (tmp)

	: [ov] "Jr" (oldval), [nv] "Jr" (newval), [e] "i" (-EFAULT)

	: "memory");

	__disable_user_access();



	*uval = val;

	return ret;

}



#endif /* CONFIG_RISCV_ISA_A */

#endif /* _ASM_FUTEX_H */