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Commit b8d2798f authored by Linus Torvalds's avatar Linus Torvalds
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Pull clk updates from Stephen Boyd:
 "This is a fairly quiet release. We don't have any patches to the core
  framework. The only patch that can even be considered "core" adds
  another clk_get() variant. The rest of the changes are in drivers for
  various SoCs, and we have a few bits for ARM shmobile architecture
  code (dts and mach) due to the dependency we're breaking between
  shmobile architecture code and its clk driver. Those shmobile bits
  have also been pulled into arm-soc tree. Here's the summary:

  Core:

   - Support for devm_get_clk_from_child() used with DT bindings that
     have subnodes with the 'clocks' property

  New Drivers:

   - Allwinner A64 (sun50i)
   - i.MX imx6ull
   - Socionext's UniPhier SoC CPUs
   - Mediatek MT2701 SoCs
   - Rockchip rk1108 SoCs
   - Qualcomm MSM8994/MSM8992 SoCS
   - Qualcomm RPM Clocks
   - Hisilicon Hi3516CV300 and Hi3798CV200 CRG
   - Oxford Semiconductor OX820 and OX810SE SoCs
   - Renesas RZ/G1M and RZ/GIE SoCs
   - Renesas R-Car RST driver for mode pin states

  Updates:

   - Four Allwinner SoCs are migrated to the new style clk driver
   - Rockchip rk3399,rk3066 PLL optimizations
   - i.MX LVDS display glitch fixes and AV PLL precision improvements
   - Qualcomm MSM8996 GPU GDSCs, hw controlled GDSCs, and Alpha PLL
     support
   - Explicit demodularization of always builtin drivers
   - Freescale Qoriq ls1012a and ls1046a support
   - Exynos 5433 parent typo fix and critical clock tagging
   - Renesas r8a7743/r8a7745 CPG
   - Renesas R-Car M3-W CSI2/VIN/SYS-DMAC/(H)SCIF/I2C/DRIF/gfx support
   - stm32f4* LSI, LSE, RTC, and QSPI clocks
   - pxa27x and pxa25x cpufreq as clks
   - TI omap36xx sprz319 advisory 2.1 workaround
   - Broadcom bcm2835 rate change propogation to PLLH_AUX from VEC"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits)
  clk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_prate()
  clk: add devm_get_clk_from_child() API
  clk: st: clk-flexgen: Unmap region obtained by of_iomap
  clk: keystone: pll: Unmap region obtained by of_iomap
  clk:mmp:clk-of-mmp2: Free memory and Unmap region obtained by kzalloc and of_iomap
  clk:mmp:clk-of-pxa910: Free memory and Unmap region obtained by kzmalloc and of_iomap
  clk: mmp: clk-of-pxa1928: Free memory obtained by kzalloc
  clk: cdce925: Fix limit check
  clk: bcm: Make COMMON_CLK_IPROC into a library
  clk: qoriq: added ls1012a clock configuration
  clk: ti: dra7: fix "failed to lookup clock node gmac_gmii_ref_clk_div" boot message
  clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock
  clk: bcm: Support rate change propagation on bcm2835 clocks
  clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clk
  clk: ti: omap36xx: Work around sprz319 advisory 2.1
  clk: clk-wm831x: fix a logic error
  clk: uniphier: add cpufreq data for LD11, LD20 SoCs
  clk: uniphier: add CPU-gear change (cpufreq) support
  clk: qcom: Put venus core0/1 gdscs to hw control mode
  clk: qcom: gdsc: Add support for gdscs with HW control
  ...
parents 96128810 2aab7a20
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+10 −3
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@@ -79,7 +79,7 @@ Required Properties:
	Input clocks for fsys clock controller:
		- oscclk
		- sclk_ufs_mphy
		- div_aclk_fsys_200
		- aclk_fsys_200
		- sclk_pcie_100_fsys
		- sclk_ufsunipro_fsys
		- sclk_mmc2_fsys
@@ -104,6 +104,10 @@ Required Properties:
		- sclk_decon_tv_vclk_disp
		- aclk_disp_333

	Input clocks for audio clock controller:
		- oscclk
		- fout_aud_pll

	Input clocks for bus0 clock controller:
		- aclk_bus0_400

@@ -235,7 +239,7 @@ Example 2: Examples of clock controller nodes are listed below.

		clock-names = "oscclk",
			"sclk_ufs_mphy",
			"div_aclk_fsys_200",
			"aclk_fsys_200",
			"sclk_pcie_100_fsys",
			"sclk_ufsunipro_fsys",
			"sclk_mmc2_fsys",
@@ -245,7 +249,7 @@ Example 2: Examples of clock controller nodes are listed below.
			"sclk_usbdrd30_fsys";
		clocks = <&xxti>,
		       <&cmu_cpif CLK_SCLK_UFS_MPHY>,
		       <&cmu_top CLK_DIV_ACLK_FSYS_200>,
		       <&cmu_top CLK_ACLK_FSYS_200>,
		       <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
		       <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
		       <&cmu_top CLK_SCLK_MMC2_FSYS>,
@@ -297,6 +301,9 @@ Example 2: Examples of clock controller nodes are listed below.
		compatible = "samsung,exynos5433-cmu-aud";
		reg = <0x114c0000 0x0b04>;
		#clock-cells = <1>;

		clock-names = "oscclk", "fout_aud_pll";
		clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
	};

	cmu_bus0: clock-controller@13600000 {
+8 −4
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* Hisilicon Hi3519 Clock and Reset Generator(CRG)
* HiSilicon Clock and Reset Generator(CRG)

The Hi3519 CRG module provides clock and reset signals to various
controllers within the SoC.
The CRG module provides clock and reset signals to various
modules within the SoC.

This binding uses the following bindings:
    Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -10,7 +10,11 @@ This binding uses the following bindings:
Required Properties:

- compatible: should be one of the following.
  - "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
  - "hisilicon,hi3516cv300-crg"
  - "hisilicon,hi3516cv300-sysctrl"
  - "hisilicon,hi3519-crg"
  - "hisilicon,hi3798cv200-crg"
  - "hisilicon,hi3798cv200-sysctrl"

- reg: physical base address of the controller and length of memory mapped
  region.
+6 −13
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@@ -5,22 +5,15 @@ Please also refer to clock-bindings.txt in this directory for common clock
bindings usage.

Required properties:
- compatible: Should be "oxsemi,ox810se-stdclk"
- compatible: For OX810SE, should be "oxsemi,ox810se-stdclk"
	      For OX820, should be "oxsemi,ox820-stdclk"
- #clock-cells: 1, see below

Parent node should have the following properties :
- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"

For OX810SE, the clock indices are :
 - 0: LEON
 - 1: DMA_SGDMA
 - 2: CIPHER
 - 3: SATA
 - 4: AUDIO
 - 5: USBMPH
 - 6: ETHA
 - 7: PCIA
 - 8: NAND
- compatible: For OX810SE, should be
		"oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
	      For OX820, should be
		"oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd"

example:

+1 −0
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@@ -14,6 +14,7 @@ Required properties :
			"qcom,gcc-msm8974"
			"qcom,gcc-msm8974pro"
			"qcom,gcc-msm8974pro-ac"
			"qcom,gcc-msm8994"
			"qcom,gcc-msm8996"
			"qcom,gcc-mdm9615"

+37 −0
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Qualcomm RPM Clock Controller Binding
------------------------------------------------
The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.

Required properties :
- compatible : shall contain only one of the following. The generic
               compatible "qcom,rpmcc" should be also included.

			"qcom,rpmcc-msm8916", "qcom,rpmcc"
			"qcom,rpmcc-apq8064", "qcom,rpmcc"

- #clock-cells : shall contain 1

Example:
	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <0 168 1>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests {
				compatible = "qcom,rpm-msm8916";
				qcom,smd-channels = "rpm_requests";

				rpmcc: clock-controller {
					compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
					#clock-cells = <1>;
				};
			};
		};
	};
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