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Commit b852f63a authored by Tal Gilboa's avatar Tal Gilboa Committed by Bjorn Helgaas
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PCI: Add pcie_bandwidth_capable() to compute max supported link bandwidth 



Add pcie_bandwidth_capable() to compute the max link bandwidth supported by
a device, based on the max link speed and width, adjusted by the encoding
overhead.

The maximum bandwidth of the link is computed as:

  max_link_width * max_link_speed * (1 - encoding_overhead)

2.5 and 5.0 GT/s links use 8b/10b encoding, which reduces the raw bandwidth
available by 20%; 8.0 GT/s and faster links use 128b/130b encoding, which
reduces it by about 1.5%.

The result is in Mb/s, i.e., megabits/second, of raw bandwidth.

Signed-off-by: default avatarTal Gilboa <talgi@mellanox.com>
[bhelgaas: add 16 GT/s, adjust for pcie_get_speed_cap() and
pcie_get_width_cap() signatures, don't export outside drivers/pci]
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent c70b65fb

drivers/pci/pci.c

+22 −0
Original line number Diff line number Diff line
@@ -5208,6 +5208,28 @@ enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) 
	return PCIE_LNK_WIDTH_UNKNOWN;

}



/**

 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability

 * @dev: PCI device

 * @speed: storage for link speed

 * @width: storage for link width

 *

 * Calculate a PCI device's link bandwidth by querying for its link speed

 * and width, multiplying them, and applying encoding overhead.  The result

 * is in Mb/s, i.e., megabits/second of raw bandwidth.

 */

u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,

			   enum pcie_link_width *width)

{

	*speed = pcie_get_speed_cap(dev);

	*width = pcie_get_width_cap(dev);



	if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)

		return 0;



	return *width * PCIE_SPEED2MBS_ENC(*speed);

}



/**

 * pci_select_bars - Make BAR mask from the type of resource

 * @dev: the PCI device for which BAR mask is made

drivers/pci/pci.h

+10 −0
Original line number Diff line number Diff line
@@ -261,8 +261,18 @@ void pci_disable_bridge_window(struct pci_dev *dev); 
	 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \

	 "Unknown speed")



/* PCIe speed to Mb/s reduced by encoding overhead */

#define PCIE_SPEED2MBS_ENC(speed) \

	((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \

	 (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \

	 (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \

	 (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \

	 0)



enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);

enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);

u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,

			   enum pcie_link_width *width);



/* Single Root I/O Virtualization */

struct pci_sriov {