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Commit b83db1de authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm/radeon/kms: enable unmappable vram for evergreen
  drm/radeon/kms: fix tiled db height calculation on 6xx/7xx
  drm/radeon/kms: fix handling of tex lookup disable in cs checker on r2xx
parents 7d2f280e 7e942503

drivers/gpu/drm/radeon/evergreen_blit_kms.c

+2 −0
Original line number Diff line number Diff line
@@ -495,6 +495,7 @@ int evergreen_blit_init(struct radeon_device *rdev) 
		dev_err(rdev->dev, "(%d) pin blit object failed\n", r);

		return r;

	}

	rdev->mc.active_vram_size = rdev->mc.real_vram_size;

	return 0;

}
@@ -502,6 +503,7 @@ void evergreen_blit_fini(struct radeon_device *rdev) 
{

	int r;



	rdev->mc.active_vram_size = rdev->mc.visible_vram_size;

	if (rdev->r600_blit.shader_obj == NULL)

		return;

	/* If we can't reserve the bo, unref should be enough to destroy

drivers/gpu/drm/radeon/r100.c

+3 −0
Original line number Diff line number Diff line
@@ -3180,6 +3180,8 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev, 
	for (u = 0; u < track->num_texture; u++) {

		if (!track->textures[u].enabled)

			continue;

		if (track->textures[u].lookup_disable)

			continue;

		robj = track->textures[u].robj;

		if (robj == NULL) {

			DRM_ERROR("No texture bound to unit %u\n", u);
@@ -3414,6 +3416,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track 
		track->textures[i].robj = NULL;

		/* CS IB emission code makes sure texture unit are disabled */

		track->textures[i].enabled = false;

		track->textures[i].lookup_disable = false;

		track->textures[i].roundup_w = true;

		track->textures[i].roundup_h = true;

		if (track->separate_cube)

drivers/gpu/drm/radeon/r100_track.h

+1 −0
Original line number Diff line number Diff line
@@ -46,6 +46,7 @@ struct r100_cs_track_texture { 
	unsigned		height_11;

	bool			use_pitch;

	bool			enabled;

	bool                    lookup_disable;

	bool			roundup_w;

	bool			roundup_h;

	unsigned                compress_format;

drivers/gpu/drm/radeon/r200.c

+2 −0
Original line number Diff line number Diff line
@@ -447,6 +447,8 @@ int r200_packet0_check(struct radeon_cs_parser *p, 
			track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);

			track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);

		}

		if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)

			track->textures[i].lookup_disable = true;

		switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {

		case R200_TXFORMAT_I8:

		case R200_TXFORMAT_RGB332:

drivers/gpu/drm/radeon/r600_cs.c

+8 −6
Original line number Diff line number Diff line
@@ -310,7 +310,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) 
	/* Check depth buffer */

	if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||

		G_028800_Z_ENABLE(track->db_depth_control)) {

		u32 nviews, bpe, ntiles, pitch, pitch_align, height, size;

		u32 nviews, bpe, ntiles, pitch, pitch_align, height, size, slice_tile_max;

		if (track->db_bo == NULL) {

			dev_warn(p->dev, "z/stencil with no depth buffer\n");

			return -EINVAL;
@@ -354,11 +354,11 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) 
		} else {

			size = radeon_bo_size(track->db_bo);

			pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;

			height = size / (pitch * 8 * bpe);

			height &= ~0x7;

			if (!height)

				height = 8;



			slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;

			slice_tile_max *= 64;

			height = slice_tile_max / (pitch * 8);

			if (height > 8192)

				height = 8192;

			switch (G_028010_ARRAY_MODE(track->db_depth_info)) {

			case V_028010_ARRAY_1D_TILED_THIN1:

				pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
@@ -367,6 +367,8 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) 
						 __func__, __LINE__, pitch);

					return -EINVAL;

				}

				/* don't break userspace */

				height &= ~0x7;

				if (!IS_ALIGNED(height, 8)) {

					dev_warn(p->dev, "%s:%d db height (%d) invalid\n",

						 __func__, __LINE__, height);