Commit b7d10841 authored Jan 19, 2019 by Martin Blumenstingl Committed by Kevin Hilman Feb 11, 2019

ARM: dts: meson8b: ec100: enable the Ethernet PHY interrupt



The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad
on the SoC.
Enable the interrupt function of the PHY's INTR32 pin to switch it from
it's default "receive error" mode to "interrupt pin" mode.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

parent e7e871b5

arch/arm/boot/dts/meson8b-ec100.dts

+4 −0

Original line number	Diff line number	Diff line
		@@ -169,6 +169,10 @@
		eth_phy0: ethernet-phy@0 {
		/* IC Plus IP101A/G (0x02430c54) */
		reg = <0>;
		icplus,select-interrupt;
		interrupt-parent = <&gpio_intc>;
		/* GPIOH_3 */
		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
		};
		};
		};