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Commit b776eec1 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'tegra-for-3.17-pcie-regulators' of... 

Merge tag 'tegra-for-3.17-pcie-regulators' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

Merge "ARM: tegra: rework PCIe regulators" from Thierry Reding:

This branch reworks the set of regulators that the Tegra PCIe driver
uses, so that the driver and DT bindings more correctly model what's
really going on in HW. For backwards-compatibility the driver will
fallback to using the old set of regulators if the new ones can't be
found.

I've made this a separate branch in case it needs to be pulled into the
PCIe tree to resolve any conflicts.

* tag 'tegra-for-3.17-pcie-regulators' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux

:
  ARM: tegra: Remove legacy PCIe power supply properties
  PCI: tegra: Remove deprecated power supply properties
  PCI: tegra: Implement accurate power supply scheme
  ARM: tegra: Add new PCIe regulator properties
  PCI: tegra: Overhaul regulator usage

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 25f00328 122ee17d

Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt

+27 −3
Original line number Diff line number Diff line
@@ -14,9 +14,6 @@ Required properties: 
- interrupt-names: Must include the following entries:

  "intr": The Tegra interrupt that is asserted for controller interrupts

  "msi": The Tegra interrupt that is asserted when an MSI is received

- pex-clk-supply: Supply voltage for internal reference clock

- vdd-supply: Power supply for controller (1.05V)

- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)

- bus-range: Range of bus numbers associated with this controller

- #address-cells: Address representation for root ports (must be 3)

  - cell 0 specifies the bus and device numbers of the root port:
@@ -60,6 +57,33 @@ Required properties: 
  - afi

  - pcie_x



Power supplies for Tegra20:

- avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.

- vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.

- avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must

  supply 1.05 V.

- avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must

  supply 1.05 V.

- vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.



Power supplies for Tegra30:

- Required:

  - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must

    supply 1.05 V.

  - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must

    supply 1.05 V.

  - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must

    supply 1.8 V.

  - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.

    Must supply 3.3 V.

- Optional:

  - If lanes 0 to 3 are used:

    - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.

    - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.

  - If lanes 4 or 5 are used:

    - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.

    - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.



Root ports are defined as subnodes of the PCIe controller node.



Required properties:

arch/arm/boot/dts/tegra20-harmony.dts

+6 −2
Original line number Diff line number Diff line
@@ -562,10 +562,14 @@ 
	};



	pcie-controller@80003000 {

		pex-clk-supply = <&pci_clk_reg>;

		vdd-supply = <&pci_vdd_reg>;

		status = "okay";



		avdd-pex-supply = <&pci_vdd_reg>;

		vdd-pex-supply = <&pci_vdd_reg>;

		avdd-pex-pll-supply = <&pci_vdd_reg>;

		avdd-plle-supply = <&pci_vdd_reg>;

		vddio-pex-clk-supply = <&pci_clk_reg>;



		pci@1,0 {

			status = "okay";

		};

arch/arm/boot/dts/tegra20-tamonten.dtsi

+5 −2
Original line number Diff line number Diff line
@@ -473,8 +473,11 @@ 
	};



	pcie-controller@80003000 {

		pex-clk-supply = <&pci_clk_reg>;

		vdd-supply = <&pci_vdd_reg>;

		avdd-pex-supply = <&pci_vdd_reg>;

		vdd-pex-supply = <&pci_vdd_reg>;

		avdd-pex-pll-supply = <&pci_vdd_reg>;

		avdd-plle-supply = <&pci_vdd_reg>;

		vddio-pex-clk-supply = <&pci_clk_reg>;

	};



	usb@c5008000 {

arch/arm/boot/dts/tegra20-trimslice.dts

+6 −2
Original line number Diff line number Diff line
@@ -318,8 +318,12 @@ 


	pcie-controller@80003000 {

		status = "okay";

		pex-clk-supply = <&pci_clk_reg>;

		vdd-supply = <&pci_vdd_reg>;



		avdd-pex-supply = <&pci_vdd_reg>;

		vdd-pex-supply = <&pci_vdd_reg>;

		avdd-pex-pll-supply = <&pci_vdd_reg>;

		avdd-plle-supply = <&pci_vdd_reg>;

		vddio-pex-clk-supply = <&pci_clk_reg>;



		pci@1,0 {

			status = "okay";

arch/arm/boot/dts/tegra30-beaver.dts

+9 −3
Original line number Diff line number Diff line
@@ -17,9 +17,15 @@ 


	pcie-controller@00003000 {

		status = "okay";

		pex-clk-supply = <&sys_3v3_pexs_reg>;

		vdd-supply = <&ldo1_reg>;

		avdd-supply = <&ldo2_reg>;



		avdd-pexa-supply = <&ldo1_reg>;

		vdd-pexa-supply = <&ldo1_reg>;

		avdd-pexb-supply = <&ldo1_reg>;

		vdd-pexb-supply = <&ldo1_reg>;

		avdd-pex-pll-supply = <&ldo1_reg>;

		avdd-plle-supply = <&ldo1_reg>;

		vddio-pex-ctl-supply = <&sys_3v3_reg>;

		hvdd-pex-supply = <&sys_3v3_pexs_reg>;



		pci@1,0 {

			status = "okay";