Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b770fe0a authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: ipa3: enable ipa register save when device is about to crash"

parents a17d83f9 8918458f

config/dataipa.h

+8 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#define CONFIG_GSI 1
@@ -8,3 +9,8 @@ 
#define CONFIG_RMNET_IPA3 1

#define CONFIG_RNDIS_IPA 1

#define CONFIG_IPA_WDI_UNIFIED_API 1

#define CONFIG_IPA3_REGDUMP 1

#define CONFIG_IPA3_APPS_REGDUMP 1

#define CONFIG_IPA3_REGDUMP_IPA_4_5 1

#define CONFIG_IPA3_4_5_RGSTR 0

#define CONFIG_IPA3_REGDUMP_NUM_EXTRA_ENDP_REGS 0

config/dataipa_GKI.conf

+4 −0
Original line number Diff line number Diff line
@@ -4,3 +4,7 @@ export CONFIG_IPA_CLIENTS_MANAGER=m 
export CONFIG_IPA_WDI_UNIFIED_API=y

export CONFIG_RMNET_IPA3=y

export CONFIG_RNDIS_IPA=m

export CONFIG_IPA3_REGDUMP=y

export CONFIG_IPA3_APPS_REGDUMP=y

export CONFIG_IPA3_REGDUMP_IPA_4_5=y

export CONFIG_IPA3_4_5_RGSTR=n

config/dataipa_QGKI.conf

+4 −0
Original line number Diff line number Diff line
@@ -4,3 +4,7 @@ export CONFIG_IPA_CLIENTS_MANAGER=y 
export CONFIG_IPA_WDI_UNIFIED_API=y

export CONFIG_RMNET_IPA3=y

export CONFIG_RNDIS_IPA=y

export CONFIG_IPA3_REGDUMP=y

export CONFIG_IPA3_APPS_REGDUMP=y

export CONFIG_IPA3_REGDUMP_IPA_4_5=y

export CONFIG_IPA3_4_5_RGSTR=n

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.1/ipa_hw_common_ex.h

+62 −2
Original line number Diff line number Diff line 
/* Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.

 *

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -412,6 +414,20 @@ enum ipa_hw_irq_srcs_e { 
 */

#define IPA_HW_REG_SAVE_NUM_ACTIVE_PIPES             23





/*

 * Total number of channel contexts that need to be saved for q6

 */



#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6         11



/*

 * Total number of event ring contexts that need to be saved for Q6

 */



#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6         11





/*

 * Macro to set the active flag for all active pipe indexed register

 */
@@ -511,7 +527,29 @@ enum ipa_hw_irq_srcs_e { 
	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[3].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 4), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[4].var_name }

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[4].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[6].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[7].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[8].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[9].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \

		(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[10].var_name }



#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
@@ -545,7 +583,29 @@ enum ipa_hw_irq_srcs_e { 
	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 2), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[2].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[3].var_name }

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[3].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[4].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[5].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[6].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[7].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[8].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[9].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[10].var_name }



/*

 * Macro to define a particular register cfg entry for all pipe

drivers/platform/msm/ipa/ipa_v3/dump/ipa4.5/ipa_hw_common_ex.h

+64 −4
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 *

 */

#if !defined(_IPA_HW_COMMON_EX_H_)

#define _IPA_HW_COMMON_EX_H_
@@ -447,6 +449,11 @@ enum ipa_hw_irq_srcs_e { 
 */

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_UC          2



/*

 * Total number of channel contexts that need to be saved for q6

 */

#define IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6         11



/*

 * Total number of event ring contexts that need to be saved for APPS

 */
@@ -456,6 +463,10 @@ enum ipa_hw_irq_srcs_e { 
 * Total number of event ring contexts that need to be saved for UC

 */

#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC         1

/*

 * Total number of event ring contexts that need to be saved for Q6

 */

#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6         11



/*

 * Total number of endpoints for which ipa_reg_save.pipes[endp_number]
@@ -562,7 +573,31 @@ enum ipa_hw_irq_srcs_e { 
       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1),  \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[0].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \

              (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[6].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[7].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[8].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[9].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \

               (u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[10].var_name }







#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 0), \
@@ -604,14 +639,39 @@ enum ipa_hw_irq_srcs_e { 
       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_A7_EE, 18), \

               (u32 *)&ipa_reg_save.gsi.evt_cntxt.a7[18].var_name }, \

       { GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \

               (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }

               (u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[4].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[5].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[6].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[7].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[8].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[9].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[10].var_name }, \

	{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 11), \

		(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[11].var_name }





/*

 * Macro to define a particular register cfg entry for all pipe

 * indexed register

 */

#define IPA_REG_SAVE_CFG_ENTRY_PIPE_ENDP(reg_name, var_name)	\

	({ GEN_1xVECTOR_REG_OFST(reg_name, 0), \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 0), \

		(u32 *)&ipa_reg_save.ipa.pipes[0].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 1), \

		(u32 *)&ipa_reg_save.ipa.pipes[1].endp.var_name }, \
@@ -672,7 +732,7 @@ enum ipa_hw_irq_srcs_e { 
	{ GEN_1xVECTOR_REG_OFST(reg_name, 29), \

		(u32 *)&ipa_reg_save.ipa.pipes[29].endp.var_name }, \

	{ GEN_1xVECTOR_REG_OFST(reg_name, 30), \

		(u32 *)&ipa_reg_save.ipa.pipes[30].endp.var_name })

		(u32 *)&ipa_reg_save.ipa.pipes[30].endp.var_name }



/*

 * Macro to define a particular register cfg entry for the remaining