Merge branch 'spi-5.4' into spi-next

* Nuvoton FLASH Interface Unit (FIU) SPI Controller

NPCM FIU supports single, dual and quad communication interface.

The NPCM7XX supports three FIU modules,

FIU0 and FIUx supports two chip selects,

FIU3 support four chip select.

Required properties:

  - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC

  - #address-cells : should be 1.

  - #size-cells : should be 0.

  - reg : the first contains the register location and length,

          the second contains the memory mapping address and length

  - reg-names: Should contain the reg names "control" and "memory"

  - clocks : phandle of FIU reference clock.

Required properties in case the pins can be muxed:

  - pinctrl-names : a pinctrl state named "default" must be defined.

  - pinctrl-0 : phandle referencing pin configuration of the device.

Optional property:

  - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.

Aliases:

- All the FIU controller nodes should be represented in the aliases node using

  the following format 'fiu{n}' where n is a unique number for the alias.

  In the NPCM7XX BMC:

  		fiu0 represent fiu 0 controller

  		fiu1 represent fiu 3 controller

  		fiu2 represent fiu x controller

Example:

fiu3: spi@c00000000 {

	compatible = "nuvoton,npcm750-fiu";

	#address-cells = <1>;

	#size-cells = <0>;

	reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;

	reg-names = "control", "memory";

	clocks = <&clk NPCM7XX_CLK_AHB>;

	pinctrl-names = "default";

	pinctrl-0 = <&spi3_pins>;

	spi-nor@0 {

			...

	};

};

Required properties:

  - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",

		 "fsl,imx7d-qspi", "fsl,imx6ul-qspi",

		 "fsl,ls1021a-qspi"

		 "fsl,ls1021a-qspi", "fsl,ls2080a-qspi"

		 or

		 "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi",

		 "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi"

  - reg : the first contains the register location and length,

          the second contains the memory mapping address and length

	clock-names = "qspi_en", "qspi";

	flash0: s25fl128s@0 {

		....

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "spansion,s25fl128s", "jedec,spi-nor";

		spi-max-frequency = <50000000>;

		reg = <0>;

	};

};

    - mediatek,mt2701-spi: for mt2701 platforms

    - mediatek,mt2712-spi: for mt2712 platforms

    - mediatek,mt6589-spi: for mt6589 platforms

    - mediatek,mt6765-spi: for mt6765 platforms

    - mediatek,mt7622-spi: for mt7622 platforms

    - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms

    - mediatek,mt8135-spi: for mt8135 platforms

ADI registers will make ADI controller registers chaos to lead incorrect results.

Then we need one hardware spinlock to synchronize between the multiple subsystems.

The new version ADI controller supplies multiple master channels for different

subsystem accessing, that means no need to add hardware spinlock to synchronize,

thus change the hardware spinlock support to be optional to keep backward

compatibility.

Required properties:

- compatible: Should be "sprd,sc9860-adi".

- reg: Offset and length of ADI-SPI controller register space.

- hwlocks: Reference to a phandle of a hwlock provider node.

- hwlock-names: Reference to hwlock name strings defined in the same order

	as the hwlocks, should be "adi".

- #address-cells: Number of cells required to define a chip select address

	on the ADI-SPI bus. Should be set to 1.

- #size-cells: Size of cells required to define a chip select address size

	on the ADI-SPI bus. Should be set to 0.

Optional properties:

- hwlocks: Reference to a phandle of a hwlock provider node.

- hwlock-names: Reference to hwlock name strings defined in the same order

	as the hwlocks, should be "adi".

- sprd,hw-channels: This is an array of channel values up to 49 channels.

	The first value specifies the hardware channel id which is used to

	transfer data triggered by hardware automatically, and the second

};

static struct gpiod_lookup_table edb93xx_spi_cs_gpio_table = {

	.dev_id = "ep93xx-spi.0",

	.dev_id = "spi0",

	.table = {

		GPIO_LOOKUP("A", 6, "cs", GPIO_ACTIVE_LOW),

		{ },