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Commit b7648c3c authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "cnss2: Add debug dump for Wlan FW PBL and SBL"

parents a665d68f 5f1e731e

drivers/net/wireless/cnss2/pci.c

+62 −21
Original line number Diff line number Diff line
@@ -74,9 +74,6 @@ static DEFINE_SPINLOCK(time_sync_lock); 


#define LINK_TRAINING_RETRY_MAX_TIMES		3



#define CNSS_DEBUG_DUMP_SRAM_START		0x1403D58

#define CNSS_DEBUG_DUMP_SRAM_SIZE		10



#define HANG_DATA_LENGTH		384

#define HST_HANG_DATA_OFFSET		((3 * 1024 * 1024) - HANG_DATA_LENGTH)

#define HSP_HANG_DATA_OFFSET		((2 * 1024 * 1024) - HANG_DATA_LENGTH)
@@ -1708,6 +1705,63 @@ static void cnss_pci_collect_dump(struct cnss_pci_data *pci_priv) 
}

#endif



/**

 * cnss_pci_dump_bl_sram_mem - Dump WLAN FW bootloader debug log

 * @pci_priv: PCI device private data structure of cnss platform driver

 *

 * Dump Primary and secondary bootloader debug log data. For SBL check the

 * log struct address and size for validity.

 *

 * Return: None

 */

static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)

{

	int i;

	u32 mem_addr, val, pbl_stage, sbl_log_start, sbl_log_size;

	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;



	if (cnss_pci_check_link_status(pci_priv))

		return;



	cnss_pci_reg_read(pci_priv, CNSS_TCSR_PBL_LOGGING_REG, &pbl_stage);

	cnss_pci_reg_read(pci_priv, CNSS_PCIE_BHI_ERRDBG2_REG, &sbl_log_start);

	cnss_pci_reg_read(pci_priv, CNSS_PCIE_BHI_ERRDBG3_REG, &sbl_log_size);

	cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x PCIE_BHI_ERRDBG: 0x%08x 0x%08x",

		    pbl_stage, sbl_log_start, sbl_log_size);



	cnss_pr_dbg("Dumping PBL log data");

	/* cnss_pci_reg_read provides 32bit register values */

	for (i = 0; i < CNSS_DEBUG_PBL_LOG_SRAM_MAX_SIZE; i += sizeof(val)) {

		mem_addr = CNSS_DEBUG_PBL_LOG_SRAM_START + i;

		if (cnss_pci_reg_read(pci_priv, mem_addr, &val))

			break;

		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);

	}



	if (plat_priv->device_version.major_version == FW_V2_NUMBER) {

		if (sbl_log_start > CNSS_SBL_DATA_START_HSP_V2 &&

		    (sbl_log_start + sbl_log_size) < CNSS_SBL_DATA_END_HSP_V2)

			goto dump_sbl_log;

	} else {

		if (sbl_log_start > CNSS_SBL_DATA_START_HSP_V1 &&

		    (sbl_log_start + sbl_log_size) < CNSS_SBL_DATA_END_HSP_V2)

			goto dump_sbl_log;

	}

	cnss_pr_err("Invalid SBL log data");

	return;



dump_sbl_log:

	cnss_pr_dbg("Dumping SBL log data");

	sbl_log_size = (sbl_log_size > CNSS_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?

			CNSS_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);

	for (i = 0; i < sbl_log_size; i += sizeof(val)) {

		mem_addr = sbl_log_start + i;

		if (cnss_pci_reg_read(pci_priv, mem_addr, &val))

			break;

		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);

	}

}



static int cnss_qca6174_powerup(struct cnss_pci_data *pci_priv)

{

	int ret = 0;
@@ -2171,8 +2225,10 @@ int cnss_wlan_register_driver(struct cnss_wlan_driver *driver_ops) 
					  msecs_to_jiffies(timeout));

	if (!ret) {

		cnss_pr_err("Timeout waiting for calibration to complete\n");

		if (!test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state))

		if (!test_bit(CNSS_IN_REBOOT, &plat_priv->driver_state)) {

			cnss_pci_dump_bl_sram_mem(pci_priv);

			CNSS_ASSERT(0);

		}



		cal_info = kzalloc(sizeof(*cal_info), GFP_KERNEL);

		if (!cal_info)
@@ -3822,21 +3878,6 @@ static void cnss_pci_dump_ce_reg(struct cnss_pci_data *pci_priv, 
	}

}



static void cnss_pci_dump_sram_mem(struct cnss_pci_data *pci_priv)

{

	int i;

	u32 mem_addr, val;



	if (cnss_pci_check_link_status(pci_priv))

		return;

	for (i = 0; i < CNSS_DEBUG_DUMP_SRAM_SIZE; i++) {

		mem_addr = CNSS_DEBUG_DUMP_SRAM_START + i * 4;

		if (cnss_pci_reg_read(pci_priv, mem_addr, &val))

			return;

		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);

	}

}



static void cnss_pci_dump_registers(struct cnss_pci_data *pci_priv)

{

	cnss_pr_dbg("Start to dump debug registers\n");
@@ -3869,7 +3910,7 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv) 
	cnss_auto_resume(&pci_priv->pci_dev->dev);

	cnss_pci_dump_misc_reg(pci_priv);

	cnss_pci_dump_shadow_reg(pci_priv);

	cnss_pci_dump_sram_mem(pci_priv);

	cnss_pci_dump_bl_sram_mem(pci_priv);



	ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_TRIGGER_RDDM);

	if (ret) {
@@ -4038,7 +4079,7 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic) 


	cnss_pci_dump_misc_reg(pci_priv);

	cnss_pci_dump_qdss_reg(pci_priv);

	cnss_pci_dump_sram_mem(pci_priv);

	cnss_pci_dump_bl_sram_mem(pci_priv);



	ret = mhi_download_rddm_img(pci_priv->mhi_ctrl, in_panic);

	if (ret) {

drivers/net/wireless/cnss2/reg.h

+11 −0
Original line number Diff line number Diff line
@@ -267,4 +267,15 @@ 
#define QCA6390_SYSPM_DBG_BUS_SEL_REG 0x1F82008

#define QCA6390_SYSPM_WCSSAON_SR_STATUS 0x1F8200C



#define CNSS_DEBUG_PBL_LOG_SRAM_START 0x1403D58

#define CNSS_DEBUG_PBL_LOG_SRAM_MAX_SIZE 40

#define CNSS_SBL_DATA_START_HSP_V1 0x143b000

#define CNSS_SBL_DATA_END_HSP_V1 (0x143b000 + 0x00011000)

#define CNSS_SBL_DATA_START_HSP_V2 0x1435000

#define CNSS_SBL_DATA_END_HSP_V2 (0x1435000 + 0x00011000)

#define CNSS_DEBUG_SBL_LOG_SRAM_MAX_SIZE 48

#define CNSS_TCSR_PBL_LOGGING_REG 0x01B000F8

#define CNSS_PCIE_BHI_ERRDBG2_REG 0x01E0E238

#define CNSS_PCIE_BHI_ERRDBG3_REG 0x01E0E23C



#endif