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Commit b677574b authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-imx7ulp' into clk-next 

* clk-imx7ulp:
  clk: imx: imx7ulp: add arm hsrun mode clocks support
  dt-bindings: clock: imx7ulp: add HSRUN mode related clocks
parents 2de34ed9 7128d7f7

drivers/clk/imx/clk-imx7ulp.c

+30 −1
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", }; 
static const char * const nic_sels[]		= { "firc", "ddr_clk", };

static const char * const periph_plat_sels[]	= { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };

static const char * const periph_bus_sels[]	= { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };

static const char * const arm_sels[]		= { "divcore", "dummy", "dummy", "hsrun_divcore", };



/* used by sosc/sirc/firc/ddr/spll/apll dividers */

static const struct clk_div_table ulp_div_table[] = {
@@ -102,10 +103,12 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) 


	/* scs/ddr/nic select different clock source requires that clock to be enabled first */

	clks[IMX7ULP_CLK_SYS_SEL]	= imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));

	clks[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));

	clks[IMX7ULP_CLK_NIC_SEL]	= imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels));

	clks[IMX7ULP_CLK_DDR_SEL]	= imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 1, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);



	clks[IMX7ULP_CLK_CORE_DIV]	= imx_clk_hw_divider_flags("divcore",	"scs_sel",  base + 0x14, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);

	clks[IMX7ULP_CLK_CORE_DIV]	= imx_clk_hw_divider_flags("divcore",	"scs_sel",  base + 0x14, 16, 4, CLK_SET_RATE_PARENT);

	clks[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT);



	clks[IMX7ULP_CLK_DDR_DIV]	= imx_clk_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3,

							       0, ulp_div_table, &imx_ccm_lock);
@@ -218,3 +221,29 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np) 
	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);

}

CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);



static void __init imx7ulp_clk_smc1_init(struct device_node *np)

{

	struct clk_hw_onecell_data *clk_data;

	struct clk_hw **clks;

	void __iomem *base;



	clk_data = kzalloc(sizeof(*clk_data) + sizeof(*clk_data->hws) *

			   IMX7ULP_CLK_SMC1_END, GFP_KERNEL);

	if (!clk_data)

		return;



	clk_data->num = IMX7ULP_CLK_SMC1_END;

	clks = clk_data->hws;



	/* SMC1 */

	base = of_iomap(np, 0);

	WARN_ON(!base);



	clks[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_IS_CRITICAL);



	imx_check_clk_hws(clks, clk_data->num);



	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);

}

CLK_OF_DECLARE(imx7ulp_clk_smc1, "fsl,imx7ulp-smc1", imx7ulp_clk_smc1_init);

include/dt-bindings/clock/imx7ulp-clock.h

+8 −1
Original line number Diff line number Diff line
@@ -54,8 +54,10 @@ 
#define IMX7ULP_CLK_SOSC_BUS_CLK	41

#define IMX7ULP_CLK_FIRC_BUS_CLK	42

#define IMX7ULP_CLK_SPLL_BUS_CLK	43

#define IMX7ULP_CLK_HSRUN_SYS_SEL	44

#define IMX7ULP_CLK_HSRUN_CORE_DIV	45



#define IMX7ULP_CLK_SCG1_END		44

#define IMX7ULP_CLK_SCG1_END		46



/* PCC2 */

#define IMX7ULP_CLK_DMA1		0
@@ -106,4 +108,9 @@ 


#define IMX7ULP_CLK_PCC3_END		16



/* SMC1 */

#define IMX7ULP_CLK_ARM			0



#define IMX7ULP_CLK_SMC1_END		1



#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */