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Commit b5fddb7c authored by oulijun's avatar oulijun Committed by Doug Ledford
Browse files

RDMA/hns: Add sq_invld_flg field in QP context 



In hip08 RoCE, it need to add the sq_invld_flg field
in QP context for RoCE hardware.

Signed-off-by: default avatarLijun Ou <oulijun@huawei.com>
Signed-off-by: default avatarWei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: default avatarShaobo Xu <xushaobo2@huawei.com>
Signed-off-by: default avatarYixian Liu <liuyixian@huawei.com>
Signed-off-by: default avatarDoug Ledford <dledford@redhat.com>
parent 28726461

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+2 −0
Original line number Diff line number Diff line
@@ -2042,6 +2042,8 @@ static void modify_qp_reset_to_init(struct ib_qp *ibqp, 


	roce_set_bit(qpc_mask->byte_168_irrl_idx,

		     V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);

	roce_set_bit(qpc_mask->byte_168_irrl_idx,

		     V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);

	roce_set_field(qpc_mask->byte_168_irrl_idx,

		       V2_QPC_BYTE_168_IRRL_IDX_LSB_M,

		       V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+4 −2
Original line number Diff line number Diff line
@@ -606,8 +606,10 @@ struct hns_roce_v2_qp_context { 


#define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20



#define	V2_QPC_BYTE_168_LP_SGEN_INI_S 21

#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 21)

#define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21



#define	V2_QPC_BYTE_168_LP_SGEN_INI_S 22

#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)



#define	V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24

#define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24)