Loading bengal-camera.dtsi +9 −9 Original line number Diff line number Diff line Loading @@ -616,9 +616,9 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading Loading @@ -681,9 +681,9 @@ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading Loading @@ -746,9 +746,9 @@ <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, <&gcc GCC_CAMSS_TFE_2_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading holi-camera.dtsi +9 −9 Original line number Diff line number Diff line Loading @@ -731,9 +731,9 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <300000000 0 240000000 0 300000000 0>, <426400000 0 341333333 0 460800000 0>, <466500000 0 384000000 0 576000000 0>; <300000000 0 0 0 300000000 0>, <426400000 0 0 0 460800000 0>, <466500000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading Loading @@ -795,9 +795,9 @@ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = <300000000 0 240000000 0 300000000 0>, <426400000 0 341333333 0 460800000 0>, <466500000 0 384000000 0 576000000 0>; <300000000 0 0 0 300000000 0>, <426400000 0 0 0 460800000 0>, <466500000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading Loading @@ -859,9 +859,9 @@ <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, <&gcc GCC_CAMSS_TFE_2_CLK>; clock-rates = <300000000 0 240000000 0 300000000 0>, <426400000 0 341333333 0 460800000 0>, <466500000 0 384000000 0 576000000 0>; <300000000 0 0 0 300000000 0>, <426400000 0 0 0 460800000 0>, <466500000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading scuba-camera.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -564,9 +564,9 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading Loading
bengal-camera.dtsi +9 −9 Original line number Diff line number Diff line Loading @@ -616,9 +616,9 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading Loading @@ -681,9 +681,9 @@ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading Loading @@ -746,9 +746,9 @@ <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, <&gcc GCC_CAMSS_TFE_2_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading
holi-camera.dtsi +9 −9 Original line number Diff line number Diff line Loading @@ -731,9 +731,9 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <300000000 0 240000000 0 300000000 0>, <426400000 0 341333333 0 460800000 0>, <466500000 0 384000000 0 576000000 0>; <300000000 0 0 0 300000000 0>, <426400000 0 0 0 460800000 0>, <466500000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading Loading @@ -795,9 +795,9 @@ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = <300000000 0 240000000 0 300000000 0>, <426400000 0 341333333 0 460800000 0>, <466500000 0 384000000 0 576000000 0>; <300000000 0 0 0 300000000 0>, <426400000 0 0 0 460800000 0>, <466500000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading Loading @@ -859,9 +859,9 @@ <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, <&gcc GCC_CAMSS_TFE_2_CLK>; clock-rates = <300000000 0 240000000 0 300000000 0>, <426400000 0 341333333 0 460800000 0>, <466500000 0 384000000 0 576000000 0>; <300000000 0 0 0 300000000 0>, <426400000 0 0 0 460800000 0>, <466500000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading
scuba-camera.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -564,9 +564,9 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; Loading