Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b56e9670 authored by Ariel Elior's avatar Ariel Elior Committed by David S. Miller
Browse files

bnx2x: Prepare device and initialize VF database 



At nic load of the PF, if VFs may be present, prepare the device
for the VFs. Initialize the VF database in preparation of VF arrival.

Signed-off-by: default avatarAriel Elior <ariele@broadcom.com>
Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 290ca2bb

drivers/net/ethernet/broadcom/bnx2x/bnx2x.h

+10 −0
Original line number Diff line number Diff line
@@ -1633,6 +1633,10 @@ struct bnx2x { 
	int					dcb_version;



	/* CAM credit pools */



	/* used only in sriov */

	struct bnx2x_credit_pool_obj		vlans_pool;



	struct bnx2x_credit_pool_obj		macs_pool;



	/* RX_MODE object */
@@ -1847,12 +1851,14 @@ int bnx2x_del_all_macs(struct bnx2x *bp, 


/* Init Function API  */

void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);

u32 bnx2x_get_pretend_reg(struct bnx2x *bp);

int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);

int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);

int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);

int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);

void bnx2x_read_mf_cfg(struct bnx2x *bp);



int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);



/* dmae */

void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
@@ -1864,6 +1870,7 @@ u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 
u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,

		      bool with_comp, u8 comp_type);



u8 bnx2x_is_pcie_pending(struct pci_dev *dev);



void bnx2x_calc_fc_adv(struct bnx2x *bp);

int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
@@ -1888,6 +1895,9 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 
	return val;

}



void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,

			    bool is_pf);



#define BNX2X_ILT_ZALLOC(x, y, size) \

	do { \

		x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \

drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c

+2 −3
Original line number Diff line number Diff line
@@ -27,8 +27,7 @@ 
#include "bnx2x_cmn.h"

#include "bnx2x_init.h"

#include "bnx2x_sp.h"





#include "bnx2x_sriov.h"



/**

 * bnx2x_move_fp - move content of the fastpath structure.
@@ -2524,7 +2523,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode) 
	/* Init per-function objects */

	if (IS_PF(bp)) {

		bnx2x_init_bp_objs(bp);



		bnx2x_iov_nic_init(bp);



		/* Set AFEX default VLAN tag to an invalid value */

		bp->afex_def_vlan_tag = -1;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h

+3 −0
Original line number Diff line number Diff line
@@ -1106,6 +1106,9 @@ static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 
	bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),

				   bnx2x_get_path_func_num(bp));



	bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1,

				    bnx2x_get_path_func_num(bp));



	/* RSS configuration object */

	bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,

				  bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),

drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

+9 −48
Original line number Diff line number Diff line
@@ -1171,7 +1171,7 @@ static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, 
	return ret;

}



static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)

u8 bnx2x_is_pcie_pending(struct pci_dev *dev)

{

	u16 status;
@@ -6269,49 +6269,6 @@ static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) 
	REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);

}



static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)

{

	u32 offset = 0;



	if (CHIP_IS_E1(bp))

		return;

	if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))

		return;



	switch (BP_ABS_FUNC(bp)) {

	case 0:

		offset = PXP2_REG_PGL_PRETEND_FUNC_F0;

		break;

	case 1:

		offset = PXP2_REG_PGL_PRETEND_FUNC_F1;

		break;

	case 2:

		offset = PXP2_REG_PGL_PRETEND_FUNC_F2;

		break;

	case 3:

		offset = PXP2_REG_PGL_PRETEND_FUNC_F3;

		break;

	case 4:

		offset = PXP2_REG_PGL_PRETEND_FUNC_F4;

		break;

	case 5:

		offset = PXP2_REG_PGL_PRETEND_FUNC_F5;

		break;

	case 6:

		offset = PXP2_REG_PGL_PRETEND_FUNC_F6;

		break;

	case 7:

		offset = PXP2_REG_PGL_PRETEND_FUNC_F7;

		break;

	default:

		return;

	}



	REG_WR(bp, offset, pretend_func_num);

	REG_RD(bp, offset);

	DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);

}



void bnx2x_pf_disable(struct bnx2x *bp)

{

	u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
@@ -6568,6 +6525,8 @@ static int bnx2x_init_hw_common(struct bnx2x *bp) 


	bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);



	bnx2x_iov_init_dmae(bp);



	/* clean the DMAE memory */

	bp->dmae_ready = 1;

	bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
@@ -7053,15 +7012,14 @@ static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) 
	REG_WR_DMAE(bp, reg, wb_write, 2);

}



static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,

				   u8 idu_sb_id, bool is_Pf)

void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)

{

	u32 data, ctl, cnt = 100;

	u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;

	u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;

	u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;

	u32 sb_bit =  1 << (idu_sb_id%32);

	u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;

	u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;

	u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;



	/* Not supported in BC mode */
@@ -7357,6 +7315,9 @@ static int bnx2x_init_hw_func(struct bnx2x *bp) 


	bnx2x_init_block(bp, BLOCK_TM, init_phase);

	bnx2x_init_block(bp, BLOCK_DORQ, init_phase);



	bnx2x_iov_init_dq(bp);



	bnx2x_init_block(bp, BLOCK_BRB1, init_phase);

	bnx2x_init_block(bp, BLOCK_PRS, init_phase);

	bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
@@ -9459,7 +9420,7 @@ static void bnx2x_period_task(struct work_struct *work) 
 * Init service functions

 */



static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)

u32 bnx2x_get_pretend_reg(struct bnx2x *bp)

{

	u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;

	u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;

drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

+18 −0
Original line number Diff line number Diff line
@@ -825,6 +825,7 @@ 
/* [RW 28] The value sent to CM header in the case of CFC load error. */

#define DORQ_REG_ERR_CMHEAD					 0x170058

#define DORQ_REG_IF_EN						 0x170004

#define DORQ_REG_MAX_RVFID_SIZE				 0x1701ec

#define DORQ_REG_MODE_ACT					 0x170008

/* [RW 5] The normal mode CID extraction offset. */

#define DORQ_REG_NORM_CID_OFST					 0x17002c
@@ -847,6 +848,22 @@ 
   writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The

   read reads this written value. */

#define DORQ_REG_RSP_INIT_CRD					 0x170048

#define DORQ_REG_RSPB_CRD_CNT					 0x1700b0

#define DORQ_REG_VF_NORM_CID_BASE				 0x1701a0

#define DORQ_REG_VF_NORM_CID_OFST				 0x1701f4

#define DORQ_REG_VF_NORM_CID_WND_SIZE				 0x1701a4

#define DORQ_REG_VF_NORM_MAX_CID_COUNT				 0x1701e4

#define DORQ_REG_VF_NORM_VF_BASE				 0x1701a8

/* [RW 10] VF type validation mask value */

#define DORQ_REG_VF_TYPE_MASK_0					 0x170218

/* [RW 17] VF type validation Min MCID value */

#define DORQ_REG_VF_TYPE_MAX_MCID_0				 0x1702d8

/* [RW 17] VF type validation Max MCID value */

#define DORQ_REG_VF_TYPE_MIN_MCID_0				 0x170298

/* [RW 10] VF type validation comp value */

#define DORQ_REG_VF_TYPE_VALUE_0				 0x170258

#define DORQ_REG_VF_USAGE_CT_LIMIT				 0x170340



/* [RW 4] Initial activity counter value on the load request; when the

   shortcut is done. */

#define DORQ_REG_SHRT_ACT_CNT					 0x170070
@@ -2571,6 +2588,7 @@ 
   current task in process). */

#define PBF_REG_DISABLE_NEW_TASK_PROC_P4			 0x14006c

#define PBF_REG_DISABLE_PF					 0x1402e8

#define PBF_REG_DISABLE_VF					 0x1402ec

/* [RW 18] For port 0: For each client that is subject to WFQ (the

 * corresponding bit is 1); indicates to which of the credit registers this

 * client is mapped. For clients which are not credit blocked; their mapping