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Commit b52c018d authored by Heiner Kallweit's avatar Heiner Kallweit Committed by David S. Miller
Browse files

net: phy: make use of new MMD accessors 



Make use of the new MMD accessors.

v2:
- fix SoB

Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1878f0dc

drivers/net/phy/dp83867.c

+17 −30
Original line number Diff line number Diff line
@@ -127,17 +127,13 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev) 
{

	struct dp83867_private *dp83867 =

		(struct dp83867_private *)phydev->priv;

	u16 val;



	val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);



	if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)

		val |= DP83867_CFG4_PORT_MIRROR_EN;

		phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,

				 DP83867_CFG4_PORT_MIRROR_EN);

	else

		val &= ~DP83867_CFG4_PORT_MIRROR_EN;



	phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);



		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,

				   DP83867_CFG4_PORT_MIRROR_EN);

	return 0;

}
@@ -222,11 +218,9 @@ static int dp83867_config_init(struct phy_device *phydev) 
	}



	/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */

	if (dp83867->rxctrl_strap_quirk) {

		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);

		val &= ~BIT(7);

		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);

	}

	if (dp83867->rxctrl_strap_quirk)

		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,

				   BIT(7));



	if (phy_interface_is_rgmii(phydev)) {

		val = phy_read(phydev, MII_DP83867_PHYCTRL);
@@ -275,17 +269,11 @@ static int dp83867_config_init(struct phy_device *phydev) 
		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,

			      delay);



		if (dp83867->io_impedance >= 0) {

			val = phy_read_mmd(phydev, DP83867_DEVADDR,

					   DP83867_IO_MUX_CFG);



			val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;

			val |= dp83867->io_impedance &

			       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;



			phy_write_mmd(phydev, DP83867_DEVADDR,

				      DP83867_IO_MUX_CFG, val);

		}

		if (dp83867->io_impedance >= 0)

			phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,

				       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL,

				       dp83867->io_impedance &

				       DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL);

	}



	/* Enable Interrupt output INT_OE in CFG3 register */
@@ -299,12 +287,11 @@ static int dp83867_config_init(struct phy_device *phydev) 
		dp83867_config_port_mirroring(phydev);



	/* Clock output selection if muxing property is set */

	if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {

		val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);

		val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;

		val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);

		phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);

	}

	if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK)

		phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,

			       DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,

			       dp83867->clk_output_sel <<

			       DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);



	return 0;

}

drivers/net/phy/dp83tc811.c

+4 −11
Original line number Diff line number Diff line
@@ -144,11 +144,8 @@ static int dp83811_set_wol(struct phy_device *phydev, 
		phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,

			      value);

	} else {

		value = phy_read_mmd(phydev, DP83811_DEVADDR,

				     MII_DP83811_WOL_CFG);

		value &= ~DP83811_WOL_EN;

		phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,

			      value);

		phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,

				   DP83811_WOL_EN);

	}



	return 0;
@@ -328,13 +325,9 @@ static int dp83811_suspend(struct phy_device *phydev) 


static int dp83811_resume(struct phy_device *phydev)

{

	int value;



	genphy_resume(phydev);



	value = phy_read_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG);



	phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, value |

	phy_set_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,

			 DP83811_WOL_CLR_INDICATION);



	return 0;

drivers/net/phy/marvell10g.c

+10 −28
Original line number Diff line number Diff line
@@ -58,24 +58,6 @@ struct mv3310_priv { 
	char *hwmon_name;

};



static int mv3310_modify(struct phy_device *phydev, int devad, u16 reg,

			 u16 mask, u16 bits)

{

	int old, val, ret;



	old = phy_read_mmd(phydev, devad, reg);

	if (old < 0)

		return old;



	val = (old & ~mask) | (bits & mask);

	if (val == old)

		return 0;



	ret = phy_write_mmd(phydev, devad, reg, val);



	return ret < 0 ? ret : 1;

}



#ifdef CONFIG_HWMON

static umode_t mv3310_hwmon_is_visible(const void *data,

				       enum hwmon_sensor_types type,
@@ -159,7 +141,7 @@ static int mv3310_hwmon_config(struct phy_device *phydev, bool enable) 
		return ret;



	val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;

	ret = mv3310_modify(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,

	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,

			     MV_V2_TEMP_CTRL_MASK, val);



	return ret < 0 ? ret : 0;
@@ -363,7 +345,7 @@ static int mv3310_config_aneg(struct phy_device *phydev) 
	linkmode_and(phydev->advertising, phydev->advertising,

		     phydev->supported);



	ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,

	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,

			     ADVERTISE_ALL | ADVERTISE_100BASE4 |

			     ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM,

			     linkmode_adv_to_mii_adv_t(phydev->advertising));
@@ -373,7 +355,7 @@ static int mv3310_config_aneg(struct phy_device *phydev) 
		changed = true;



	reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);

	ret = mv3310_modify(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,

	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,

			     ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);

	if (ret < 0)

		return ret;
@@ -387,7 +369,7 @@ static int mv3310_config_aneg(struct phy_device *phydev) 
	else

		reg = 0;



	ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,

	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,

			     MDIO_AN_10GBT_CTRL_ADV10G, reg);

	if (ret < 0)

		return ret;

drivers/net/phy/phy-c45.c

+4 −17
Original line number Diff line number Diff line
@@ -75,15 +75,9 @@ EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced); 
 */

int genphy_c45_an_disable_aneg(struct phy_device *phydev)

{

	int val;



	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);

	if (val < 0)

		return val;



	val &= ~(MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);



	return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);

	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,

				  MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);

}

EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
@@ -97,15 +91,8 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg); 
 */

int genphy_c45_restart_aneg(struct phy_device *phydev)

{

	int val;



	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);

	if (val < 0)

		return val;



	val |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART;



	return phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, val);

	return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,

				MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);

}

EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);

drivers/net/phy/phy.c

+3 −8
Original line number Diff line number Diff line
@@ -1060,17 +1060,12 @@ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable) 
		if (!phy_check_valid(phydev->speed, phydev->duplex, common))

			goto eee_exit_err;



		if (clk_stop_enable) {

		if (clk_stop_enable)

			/* Configure the PHY to stop receiving xMII

			 * clock while it is signaling LPI.

			 */

			int val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);

			if (val < 0)

				return val;



			val |= MDIO_PCS_CTRL1_CLKSTOP_EN;

			phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, val);

		}

			phy_set_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1,

					 MDIO_PCS_CTRL1_CLKSTOP_EN);



		return 0; /* EEE supported */

	}