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Commit b4e87c09 authored by Brian Norris's avatar Brian Norris Committed by Heiko Stuebner
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arm64: dts: rockchip: add sdhci/emmc for rk3399 



Add description for the SDHCI v5.1 eMMC controller on rk3399. Fix it to
200 MHz, to support all supported timing modes.

Note that 'rockchip,rk3399-sdhci-5.1' is not documented; we presumably
have a compliant Arasan controller, but let's have a rockchip property
as the canonical backup/precautionary measure. Per Heiko's previous
suggestion, let's not clutter the arasan doc with it.

Signed-off-by: default avatarBrian Norris <briannorris@chromium.org>
Reviewed-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 16759262

arch/arm64/boot/dts/rockchip/rk3399.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -215,6 +215,19 @@ 
		status = "disabled";

	};



	sdhci: sdhci@fe330000 {

		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";

		reg = <0x0 0xfe330000 0x0 0x10000>;

		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

		assigned-clocks = <&cru SCLK_EMMC>;

		assigned-clock-rates = <200000000>;

		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;

		clock-names = "clk_xin", "clk_ahb";

		phys = <&emmc_phy>;

		phy-names = "phy_arasan";

		status = "disabled";

	};



	usb_host0_ehci: usb@fe380000 {

		compatible = "generic-ehci";

		reg = <0x0 0xfe380000 0x0 0x20000>;
@@ -503,6 +516,13 @@ 
		reg = <0x0 0xff770000 0x0 0x10000>;

		#address-cells = <1>;

		#size-cells = <1>;



		emmc_phy: phy@f780 {

			compatible = "rockchip,rk3399-emmc-phy";

			reg = <0xf780 0x24>;

			#phy-cells = <0>;

			status = "disabled";

		};

	};



	watchdog@ff840000 {