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Commit b481e326 authored by Shravan Nevatia's avatar Shravan Nevatia
Browse files

ARM: dts: msm: Add CSIPHY/CCI devicetree support for shima 

Add CSIPHY/CCI nodes to camera devicetree for shima.

Change-Id: I4499e9aab45fb8f1e7728fffc5b260638d18eeff
CRs-Fixed: 2709344
parent dd390c23

shima-camera.dtsi

+390 −0
Original line number Diff line number Diff line
@@ -11,6 +11,396 @@ 
		status = "ok";

	};



	cam_csiphy0: qcom,csiphy0 {

		cell-index = <0>;

		compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";

		reg = <0x0ac6a000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x6a000>;

		interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy0";

		gdscr-supply = <&cam_cc_titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-1p2-supply = <&L10C>;

		csi-vdd-0p9-supply = <&L6B>;

		regulator-names = "gdscr", "refgen", "csi-vdd-1p2",

			"csi-vdd-0p9";

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 1200000 880000>;

		rgltr-max-voltage = <0 0 1260000 1050000>;

		rgltr-load-current = <0 0 54000 96400>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY0_CLK>,

			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy0_clk",

			"csi0phytimer_clk_src",

			"csi0phytimer_clk";

		src-clock-name = "csi0phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy1: qcom,csiphy1 {

		cell-index = <1>;

		compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";

		reg = <0xac6c000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x6c000>;

		interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy1";

		gdscr-supply = <&cam_cc_titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-1p2-supply = <&L10C>;

		csi-vdd-0p9-supply = <&L6B>;

		regulator-names = "gdscr", "refgen", "csi-vdd-1p2",

			"csi-vdd-0p9";

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 1200000 880000>;

		rgltr-max-voltage = <0 0 1260000 1050000>;

		rgltr-load-current = <0 0 54000 96400>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY1_CLK>,

			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy1_clk",

			"csi1phytimer_clk_src",

			"csi1phytimer_clk";

		src-clock-name = "csi1phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy2: qcom,csiphy2 {

		cell-index = <2>;

		compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";

		reg = <0xac6e000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x6e000>;

		interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy2";

		gdscr-supply = <&cam_cc_titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-1p2-supply = <&L10C>;

		csi-vdd-0p9-supply = <&L6B>;

		regulator-names = "gdscr", "refgen", "csi-vdd-1p2",

			"csi-vdd-0p9";

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 1200000 880000>;

		rgltr-max-voltage = <0 0 1260000 1050000>;

		rgltr-load-current = <0 0 54000 96400>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY2_CLK>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy2_clk",

			"csi2phytimer_clk_src",

			"csi2phytimer_clk";

		src-clock-name = "csi2phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy3: qcom,csiphy3 {

		cell-index = <3>;

		compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";

		reg = <0xac70000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x70000>;

		interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy3";

		gdscr-supply = <&cam_cc_titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-1p2-supply = <&L10C>;

		csi-vdd-0p9-supply = <&L6B>;

		regulator-names = "gdscr", "refgen", "csi-vdd-1p2",

			"csi-vdd-0p9";

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 1200000 880000>;

		rgltr-max-voltage = <0 0 1260000 1050000>;

		rgltr-load-current = <0 0 54000 96400>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY3_CLK>,

			<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy3_clk",

			"csi3phytimer_clk_src",

			"csi3phytimer_clk";

		src-clock-name = "csi3phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy4: qcom,csiphy4 {

		cell-index = <4>;

		compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";

		reg = <0xac72000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x72000>;

		interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy4";

		gdscr-supply = <&cam_cc_titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-1p2-supply = <&L10C>;

		csi-vdd-0p9-supply = <&L6B>;

		regulator-names = "gdscr", "refgen", "csi-vdd-1p2",

			"csi-vdd-0p9";

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 1200000 880000>;

		rgltr-max-voltage = <0 0 1260000 1050000>;

		rgltr-load-current = <0 0 54000 96400>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY4_CLK>,

			<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy4_clk",

			"csi4phytimer_clk_src",

			"csi4phytimer_clk";

		src-clock-name = "csi4phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};



	cam_csiphy5: qcom,csiphy5 {

		cell-index = <5>;

		compatible = "qcom,csiphy-v1.2.4", "qcom,csiphy";

		reg = <0xac74000 0x2000>;

		reg-names = "csiphy";

		reg-cam-base = <0x74000>;

		interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;

		interrupt-names = "csiphy5";

		gdscr-supply = <&cam_cc_titan_top_gdsc>;

		refgen-supply = <&refgen>;

		csi-vdd-1p2-supply = <&L10C>;

		csi-vdd-0p9-supply = <&L6B>;

		regulator-names = "gdscr", "refgen", "csi-vdd-1p2",

			"csi-vdd-0p9";

		rgltr-cntrl-support;

		rgltr-min-voltage = <0 0 1200000 880000>;

		rgltr-max-voltage = <0 0 1260000 1050000>;

		rgltr-load-current = <0 0 54000 96400>;

		clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,

			<&clock_camcc CAM_CC_CSIPHY5_CLK>,

			<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,

			<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>;

		clock-names = "cphy_rx_clk_src",

			"csiphy5_clk",

			"csi5phytimer_clk_src",

			"csi5phytimer_clk";

		src-clock-name = "csi5phytimer_clk_src";

		clock-cntl-level = "lowsvs", "svs";

		clock-rates =

			<320000000 0 300000000 0>,

			<400000000 0 300000000 0>;

		status = "ok";

	};



	cam_cci0: qcom,cci0 {

		cell-index = <0>;

		compatible = "qcom,cci", "simple-bus";

		reg = <0xac4f000 0x1000>;

		reg-names = "cci";

		reg-cam-base = <0x4f000>;

		interrupt-names = "cci";

		interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;

		status = "ok";

		gdscr-supply = <&cam_cc_titan_top_gdsc>;

		regulator-names = "gdscr";

		clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>,

			<&clock_camcc CAM_CC_CCI_0_CLK>;

		clock-names = "cci_0_clk_src",

			"cci_0_clk";

		src-clock-name = "cci_0_clk_src";

		clock-cntl-level = "lowsvs";

		clock-rates = <37500000 0>;

		pinctrl-names = "cam_default", "cam_suspend";

		pinctrl-0 = <&cci0_active &cci1_active>;

		pinctrl-1 = <&cci0_suspend &cci1_suspend>;

		gpios = <&tlmm 107 0>,

			<&tlmm 108 0>,

			<&tlmm 109 0>,

			<&tlmm 110 0>;

		gpio-req-tbl-num = <0 1 2 3>;

		gpio-req-tbl-flags = <1 1 1 1>;

		gpio-req-tbl-label = "CCI_I2C_DATA0",

					"CCI_I2C_CLK0",

					"CCI_I2C_DATA1",

					"CCI_I2C_CLK1";



		i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {

			hw-thigh = <201>;

			hw-tlow = <174>;

			hw-tsu-sto = <204>;

			hw-tsu-sta = <231>;

			hw-thd-dat = <22>;

			hw-thd-sta = <162>;

			hw-tbuf = <227>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_custom_cci0: qcom,i2c_custom_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <1>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {

			hw-thigh = <16>;

			hw-tlow = <22>;

			hw-tsu-sto = <17>;

			hw-tsu-sta = <18>;

			hw-thd-dat = <16>;

			hw-thd-sta = <15>;

			hw-tbuf = <24>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <3>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};

	};



	cam_cci1: qcom,cci1 {

		cell-index = <1>;

		compatible = "qcom,cci", "simple-bus";

		reg = <0xac50000 0x1000>;

		reg-names = "cci";

		reg-cam-base = <0x50000>;

		interrupt-names = "cci";

		interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;

		status = "ok";

		gdscr-supply = <&cam_cc_titan_top_gdsc>;

		regulator-names = "gdscr";

		clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>,

			<&clock_camcc CAM_CC_CCI_1_CLK>;

		clock-names = "cci_1_clk_src",

			"cci_1_clk";

		src-clock-name = "cci_1_clk_src";

		clock-cntl-level = "lowsvs";

		clock-rates = <37500000 0>;

		pinctrl-names = "cam_default", "cam_suspend";

		pinctrl-0 = <&cci2_active &cci3_active>;

		pinctrl-1 = <&cci2_suspend &cci3_suspend>;

		gpios = <&tlmm 111 0>,

			<&tlmm 112 0>,

			<&tlmm 113 0>,

			<&tlmm 114 0>;

		gpio-req-tbl-num = <0 1 2 3>;

		gpio-req-tbl-flags = <1 1 1 1>;

		gpio-req-tbl-label = "CCI_I2C_DATA2",

					"CCI_I2C_CLK2",

					"CCI_I2C_DATA3",

					"CCI_I2C_CLK3";



		i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {

			hw-thigh = <201>;

			hw-tlow = <174>;

			hw-tsu-sto = <204>;

			hw-tsu-sta = <231>;

			hw-thd-dat = <22>;

			hw-thd-sta = <162>;

			hw-tbuf = <227>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_custom_cci1: qcom,i2c_custom_mode {

			hw-thigh = <38>;

			hw-tlow = <56>;

			hw-tsu-sto = <40>;

			hw-tsu-sta = <40>;

			hw-thd-dat = <22>;

			hw-thd-sta = <35>;

			hw-tbuf = <62>;

			hw-scl-stretch-en = <1>;

			hw-trdhld = <6>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};



		i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {

			hw-thigh = <16>;

			hw-tlow = <22>;

			hw-tsu-sto = <17>;

			hw-tsu-sta = <18>;

			hw-thd-dat = <16>;

			hw-thd-sta = <15>;

			hw-tbuf = <24>;

			hw-scl-stretch-en = <0>;

			hw-trdhld = <3>;

			hw-tsp = <3>;

			cci-clk-src = <37500000>;

			status = "ok";

		};

	};



	qcom,cam_smmu {

		compatible = "qcom,msm-cam-smmu", "simple-bus";

		status = "ok";