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Commit b3cf93b3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Radeon and i915 fixes.

  I probably should have sent these earlier, but nothing too urgent in
  them:

   - i915:
        blackscreen and corruption fixes
   - radeon:
        oops, locking and stability"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/radeon: add missing crtc unlock when setting up the MC
  drm/radeon: use gart for DMA IB tests
  drm/radeon: make sure mode init is complete in bandwidth_update
  drm/radeon: set correct CE ram size for CIK
  drm/i915: safeguard against too high minimum brightness
  drm/i915: vlv: fix gunit HW state corruption during S4 suspend
  drm/i915: Disable caches for Global GTT.
parents 206c5f60 03dca708

drivers/gpu/drm/i915/i915_drv.c

+10 −0
Original line number Diff line number Diff line
@@ -986,6 +986,15 @@ static int i915_pm_freeze(struct device *dev) 
	return i915_drm_freeze(drm_dev);

}



static int i915_pm_freeze_late(struct device *dev)

{

	struct pci_dev *pdev = to_pci_dev(dev);

	struct drm_device *drm_dev = pci_get_drvdata(pdev);

	struct drm_i915_private *dev_priv = drm_dev->dev_private;



	return intel_suspend_complete(dev_priv);

}



static int i915_pm_thaw_early(struct device *dev)

{

	struct pci_dev *pdev = to_pci_dev(dev);
@@ -1570,6 +1579,7 @@ static const struct dev_pm_ops i915_pm_ops = { 
	.resume_early = i915_pm_resume_early,

	.resume = i915_pm_resume,

	.freeze = i915_pm_freeze,

	.freeze_late = i915_pm_freeze_late,

	.thaw_early = i915_pm_thaw_early,

	.thaw = i915_pm_thaw,

	.poweroff = i915_pm_poweroff,

drivers/gpu/drm/i915/i915_gem_gtt.c

+16 −0
Original line number Diff line number Diff line
@@ -1902,6 +1902,22 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) 
	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |

	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));



	if (!USES_PPGTT(dev_priv->dev))

		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,

		 * so RTL will always use the value corresponding to

		 * pat_sel = 000".

		 * So let's disable cache for GGTT to avoid screen corruptions.

		 * MOCS still can be used though.

		 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work

		 * before this patch, i.e. the same uncached + snooping access

		 * like on gen6/7 seems to be in effect.

		 * - So this just fixes blitter/render access. Again it looks

		 * like it's not just uncached access, but uncached + snooping.

		 * So we can still hold onto all our assumptions wrt cpu

		 * clflushing on LLC machines.

		 */

		pat = GEN8_PPAT(0, GEN8_PPAT_UC);



	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b

	 * write would work. */

	I915_WRITE(GEN8_PRIVATE_PAT, pat);

drivers/gpu/drm/i915/intel_panel.c

+15 −2
Original line number Diff line number Diff line
@@ -1098,12 +1098,25 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector) 
	struct drm_device *dev = connector->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_panel *panel = &connector->panel;

	int min;



	WARN_ON(panel->backlight.max == 0);



	/*

	 * XXX: If the vbt value is 255, it makes min equal to max, which leads

	 * to problems. There are such machines out there. Either our

	 * interpretation is wrong or the vbt has bogus data. Or both. Safeguard

	 * against this by letting the minimum be at most (arbitrarily chosen)

	 * 25% of the max.

	 */

	min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);

	if (min != dev_priv->vbt.backlight.min_brightness) {

		DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n",

			      dev_priv->vbt.backlight.min_brightness, min);

	}



	/* vbt value is a coefficient in range [0..255] */

	return scale(dev_priv->vbt.backlight.min_brightness, 0, 255,

		     0, panel->backlight.max);

	return scale(min, 0, 255, 0, panel->backlight.max);

}



static int bdw_setup_backlight(struct intel_connector *connector)

drivers/gpu/drm/radeon/cik.c

+5 −2
Original line number Diff line number Diff line
@@ -4313,8 +4313,8 @@ static int cik_cp_gfx_start(struct radeon_device *rdev) 
	/* init the CE partitions.  CE only used for gfx on CIK */

	radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));

	radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));

	radeon_ring_write(ring, 0xc000);

	radeon_ring_write(ring, 0xc000);

	radeon_ring_write(ring, 0x8000);

	radeon_ring_write(ring, 0x8000);



	/* setup clear context state */

	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
@@ -9447,6 +9447,9 @@ void dce8_bandwidth_update(struct radeon_device *rdev) 
	u32 num_heads = 0, lb_size;

	int i;



	if (!rdev->mode_info.mode_config_initialized)

		return;



	radeon_update_display_priority(rdev);



	for (i = 0; i < rdev->num_crtc; i++) {

drivers/gpu/drm/radeon/cik_sdma.c

+12 −9
Original line number Diff line number Diff line
@@ -667,17 +667,20 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 
{

	struct radeon_ib ib;

	unsigned i;

	unsigned index;

	int r;

	void __iomem *ptr = (void *)rdev->vram_scratch.ptr;

	u32 tmp = 0;

	u64 gpu_addr;



	if (!ptr) {

		DRM_ERROR("invalid vram scratch pointer\n");

		return -EINVAL;

	}

	if (ring->idx == R600_RING_TYPE_DMA_INDEX)

		index = R600_WB_DMA_RING_TEST_OFFSET;

	else

		index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;



	gpu_addr = rdev->wb.gpu_addr + index;



	tmp = 0xCAFEDEAD;

	writel(tmp, ptr);

	rdev->wb.wb[index/4] = cpu_to_le32(tmp);



	r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);

	if (r) {
@@ -686,8 +689,8 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 
	}



	ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);

	ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;

	ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr);

	ib.ptr[1] = lower_32_bits(gpu_addr);

	ib.ptr[2] = upper_32_bits(gpu_addr);

	ib.ptr[3] = 1;

	ib.ptr[4] = 0xDEADBEEF;

	ib.length_dw = 5;
@@ -704,7 +707,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 
		return r;

	}

	for (i = 0; i < rdev->usec_timeout; i++) {

		tmp = readl(ptr);

		tmp = le32_to_cpu(rdev->wb.wb[index/4]);

		if (tmp == 0xDEADBEEF)

			break;

		DRM_UDELAY(1);