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Commit b361bd76 authored by John Crispin's avatar John Crispin Committed by Ralf Baechle
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MIPS: ralink: Fix usb issue during frequency scaling 



If the USB HCD is running and the cpu is scaled too low, then the USB
stops working. Increase the idle speed of the core to fix this if the
kernel is built with USB support.

The "magic" values are taken from the Ralink SDK Kernel.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11441/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 418d29c8

arch/mips/ralink/mt7620.c

+20 −0
Original line number Diff line number Diff line
@@ -37,6 +37,12 @@ 
#define PMU1_CFG		0x8C

#define DIG_SW_SEL		BIT(25)



/* clock scaling */

#define CLKCFG_FDIV_MASK	0x1f00

#define CLKCFG_FDIV_USB_VAL	0x0300

#define CLKCFG_FFRAC_MASK	0x001f

#define CLKCFG_FFRAC_USB_VAL	0x0003



/* EFUSE bits */

#define EFUSE_MT7688		0x100000
@@ -432,6 +438,20 @@ void __init ralink_clk_init(void) 
	ralink_clk_add("10000b00.spi", sys_rate);

	ralink_clk_add("10000c00.uartlite", periph_rate);

	ralink_clk_add("10180000.wmac", xtal_rate);



	if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) {

		/*

		 * When the CPU goes into sleep mode, the BUS clock will be

		 * too low for USB to function properly. Adjust the busses

		 * fractional divider to fix this

		 */

		u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);



		val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);

		val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;



		rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);

	}

}



void __init ralink_of_remap(void)