Merge "clk: qcom: Fix orphaned sleep clocks for Lahaina" (b2d35600) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/clk/qcom/camcc-lahaina.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -39,8 +39,8 @@ enum {
		P_CAM_CC_PLL4_OUT_EVEN,
		P_CAM_CC_PLL5_OUT_EVEN,
		P_CAM_CC_PLL6_OUT_EVEN,
		P_CHIP_SLEEP_CLK,
		P_CORE_BI_PLL_TEST_SE,
		P_SLEEP_CLK,
		};

		static struct pll_vco lucid_5lpe_vco[] = {
		@@ -563,12 +563,12 @@ static const struct clk_parent_data cam_cc_parent_data_5[] = {
		};

		static const struct parent_map cam_cc_parent_map_6[] = {
		{ P_CHIP_SLEEP_CLK, 0 },
		{ P_SLEEP_CLK, 0 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const struct clk_parent_data cam_cc_parent_data_6[] = {
		{ .fw_name = "chip_sleep_clk", .name = "chip_sleep_clk" },
		{ .fw_name = "sleep_clk", .name = "sleep_clk" },
		{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
		};

		@@ -1410,7 +1410,7 @@ static struct clk_rcg2 cam_cc_sbi_csid_clk_src = {
		};

		static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
		F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
		F(32000, P_SLEEP_CLK, 1, 0, 0),
		{ }
		};

+4 −4

Original line number	Diff line number	Diff line
		@@ -30,7 +30,6 @@ static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);

		enum {
		P_BI_TCXO,
		P_CHIP_SLEEP_CLK,
		P_CORE_BI_PLL_TEST_SE,
		P_DISP_CC_PLL0_OUT_MAIN,
		P_DISP_CC_PLL1_OUT_EVEN,
		@@ -47,6 +46,7 @@ enum {
		P_DSI1_PHY_PLL_OUT_DSICLK,
		P_EDP_PHY_PLL_LINK_CLK,
		P_EDP_PHY_PLL_VCO_DIV_CLK,
		P_SLEEP_CLK,
		};

		static struct pll_vco lucid_5lpe_vco[] = {
		@@ -251,12 +251,12 @@ static const struct clk_parent_data disp_cc_parent_data_6[] = {
		};

		static const struct parent_map disp_cc_parent_map_7[] = {
		{ P_CHIP_SLEEP_CLK, 0 },
		{ P_SLEEP_CLK, 0 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const struct clk_parent_data disp_cc_parent_data_7[] = {
		{ .fw_name = "chip_sleep_clk", .name = "chip_sleep_clk" },
		{ .fw_name = "sleep_clk", .name = "sleep_clk" },
		{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
		};

		@@ -755,7 +755,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
		};

		static const struct freq_tbl ftbl_disp_cc_sleep_clk_src[] = {
		F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
		F(32000, P_SLEEP_CLK, 1, 0, 0),
		{ }
		};

+4 −4

Original line number	Diff line number	Diff line
		@@ -29,8 +29,8 @@ static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);

		enum {
		P_BI_TCXO,
		P_CHIP_SLEEP_CLK,
		P_CORE_BI_PLL_TEST_SE,
		P_SLEEP_CLK,
		P_VIDEO_PLL0_OUT_MAIN,
		P_VIDEO_PLL1_OUT_MAIN,
		};
		@@ -152,12 +152,12 @@ static const struct clk_parent_data video_cc_parent_data_2[] = {
		};

		static const struct parent_map video_cc_parent_map_3[] = {
		{ P_CHIP_SLEEP_CLK, 0 },
		{ P_SLEEP_CLK, 0 },
		{ P_CORE_BI_PLL_TEST_SE, 7 },
		};

		static const struct clk_parent_data video_cc_parent_data_3[] = {
		{ .fw_name = "chip_sleep_clk", .name = "chip_sleep_clk" },
		{ .fw_name = "sleep_clk", .name = "sleep_clk" },
		{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
		};

		@@ -250,7 +250,7 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = {
		};

		static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
		F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
		F(32000, P_SLEEP_CLK, 1, 0, 0),
		{ }
		};