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Commit b2bcc7b2 authored by Alok Kataria's avatar Alok Kataria Committed by H. Peter Anvin
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x86: add a synthetic TSC_RELIABLE feature bit 



Impact: None, bit reservation only

Add a synthetic TSC_RELIABLE feature bit which will be used to mark
TSC as reliable so that we could skip all the runtime checks for
TSC stablity, which have false positives in virtual environment.

Signed-off-by: default avatarAlok N Kataria <akataria@vmware.com>
Signed-off-by: default avatarDan Hecht <dhecht@vmware.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent 2576c999

arch/x86/include/asm/cpufeature.h

+1 −0
Original line number Diff line number Diff line
@@ -92,6 +92,7 @@ 
#define X86_FEATURE_NOPL	(3*32+20) /* The NOPL (0F 1F) instructions */

#define X86_FEATURE_AMDC1E	(3*32+21) /* AMD C1E detected */

#define X86_FEATURE_XTOPOLOGY	(3*32+22) /* cpu topology enum extensions */

#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */



/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */