MIPS: TXx9: Add RBTX4939 board support (b27311e1) · Commits · e / devices / android_kernel_fairphone_FP5

arch/mips/Makefile

+2 −6

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		@@ -567,15 +567,11 @@ cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434
		load-$(CONFIG_MIKROTIK_RB532) += 0xffffffff80101000

		#
		# Toshiba RBTX4927 board or
		# Toshiba RBTX4937 board
		# Toshiba RBTX49XX boards
		#
		core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/

		#
		# Toshiba RBTX4938 board
		#
		core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
		core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/

		cflags-y += -Iinclude/asm-mips/mach-generic
		drivers-$(CONFIG_PCI) += arch/mips/pci/

arch/mips/txx9/Kconfig

+8 −0

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		@@ -45,6 +45,14 @@ config TOSHIBA_RBTX4938
		This Toshiba board is based on the TX4938 processor. Say Y here to
		support this machine type

		config TOSHIBA_RBTX4939
		bool "Toshiba RBTX4939 bobard"
		depends on MACH_TX49XX
		select SOC_TX4939
		help
		This Toshiba board is based on the TX4939 processor. Say Y here to
		support this machine type

		config SOC_TX3927
		bool
		select CEVT_TXX9

arch/mips/txx9/generic/setup.c

+5 −0

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		@@ -371,6 +371,11 @@ static void __init select_board(void)
		case 0x4938:
		txx9_board_vec = &rbtx4938_vec;
		break;
		#endif
		#ifdef CONFIG_TOSHIBA_RBTX4939
		case 0x4939:
		txx9_board_vec = &rbtx4939_vec;
		break;
		#endif
		}
		#endif

arch/mips/txx9/rbtx4939/Makefile

0 → 100644

+3 −0

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		obj-y += irq.o setup.o prom.o

		EXTRA_CFLAGS += -Werror

arch/mips/txx9/rbtx4939/irq.c

0 → 100644

+96 −0

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		/*
		* Toshiba RBTX4939 interrupt routines
		* Based on linux/arch/mips/txx9/rbtx4938/irq.c,
		* and RBTX49xx patch from CELF patch archive.
		*
		* Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
		* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
		* terms of the GNU General Public License version 2. This program is
		* licensed "as is" without any warranty of any kind, whether express
		* or implied.
		*/
		#include <linux/init.h>
		#include <linux/interrupt.h>
		#include <asm/mipsregs.h>
		#include <asm/txx9/rbtx4939.h>

		/*
		* RBTX4939 IOC controller definition
		*/

		static void rbtx4939_ioc_irq_unmask(unsigned int irq)
		{
		int ioc_nr = irq - RBTX4939_IRQ_IOC;

		writeb(readb(rbtx4939_ien_addr) \| (1 << ioc_nr), rbtx4939_ien_addr);
		}

		static void rbtx4939_ioc_irq_mask(unsigned int irq)
		{
		int ioc_nr = irq - RBTX4939_IRQ_IOC;

		writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
		mmiowb();
		}

		static struct irq_chip rbtx4939_ioc_irq_chip = {
		.name = "IOC",
		.ack = rbtx4939_ioc_irq_mask,
		.mask = rbtx4939_ioc_irq_mask,
		.mask_ack = rbtx4939_ioc_irq_mask,
		.unmask = rbtx4939_ioc_irq_unmask,
		};


		static inline int rbtx4939_ioc_irqroute(void)
		{
		unsigned char istat = readb(rbtx4939_ifac2_addr);

		if (unlikely(istat == 0))
		return -1;
		return RBTX4939_IRQ_IOC + __fls8(istat);
		}

		static int rbtx4939_irq_dispatch(int pending)
		{
		int irq;

		if (pending & CAUSEF_IP7)
		return MIPS_CPU_IRQ_BASE + 7;
		irq = tx4939_irq();
		if (likely(irq >= 0)) {
		/* redirect IOC interrupts */
		switch (irq) {
		case RBTX4939_IRQ_IOCINT:
		irq = rbtx4939_ioc_irqroute();
		break;
		}
		} else if (pending & CAUSEF_IP0)
		irq = MIPS_CPU_IRQ_BASE + 0;
		else if (pending & CAUSEF_IP1)
		irq = MIPS_CPU_IRQ_BASE + 1;
		else
		irq = -1;
		return irq;
		}

		void __init rbtx4939_irq_setup(void)
		{
		int i;

		/* mask all IOC interrupts */
		writeb(0, rbtx4939_ien_addr);

		/* clear SoftInt interrupts */
		writeb(0, rbtx4939_softint_addr);

		txx9_irq_dispatch = rbtx4939_irq_dispatch;

		tx4939_irq_init();
		for (i = RBTX4939_IRQ_IOC;
		i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
		set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
		handle_level_irq);

		set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
		}